Architecture
The main features of the eSi-RISC architecture are:[3]
- RISC-like load/store architecture.
- Configurable 16-bit, 32-bit or 32/64-bit data-path.
- Instructions are encoded in either 16 or 32-bits.
- 8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide.
- 0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide.
- Up to 32 external, vectored, nested and prioritizable interrupts.
- Configurable instruction set including support for integer, floating-point and fixed-point arithmetic.
- SIMD operations.
- Optional support for user-defined instructions, such as cryptographic acceleration .[4]
- Optional caches (Configurable size and associativity).
- Optional MMU supporting both memory protection and dynamic address translation.
- AMBA AXI, AHB and APB bus interfaces.
- Memory mapped I/O.
- 5-stage pipeline.
- Hardware JTAG debug.
While there are many different 16 or 32-bit Soft microprocessor IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations.
Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are executed. This improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers.
eSi-RISC includes support for Multiprocessing. Implementations have included up to seven eSi-3250's on a single chip.[5]