The 2021 IRDS Lithography standard is a backward-facing document, as the first volume production of a "7 nm" branded process, as Taiwan Semiconductor Manufacturing Company (TSMC) began production of 256 Mbit SRAM memory chips using a "7 nm" process called N7 in June 2016,[2] before Samsung began mass production of their "7 nm" process called 7LPP devices in 2018.[3] These process nodes had the same approximate transistor density as Intel's "10 nm Enhanced Superfin" node, later rebranded "Intel 7."[4]
Since at least 1997, the length scale of a process node has not referred to any particular dimension on the integrated circuits, such as gate length, metal pitch, or gate pitch, as new lithography processes no longer uniformly shrank all features on a chip. By the late 2010s, the length scale had become a commercial name[5] that indicated a new generation of process technologies, without any relation to physical properties.[6][7][8] Previous ITRS and IRDS standards had insufficient guidance on process node naming conventions to address the widely varying dimensions on a chip, leading to divergence between how foundries branded their lithography and the actual dimensions their process nodes achieved.
The first mainstream "7 nm" mobile processor intended for mass market use, the AppleA12 Bionic, was released at Apple's September 2018 event.[9] Although Huawei announced its own "7 nm" processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips were manufactured by TSMC.[10]
In 2019,[11] AMD released their "Rome" (EPYC 2) processors for servers and datacenters, which are based on TSMC's N7node[12] and feature up to 64 cores and 128 threads. They also released their "Matisse" consumer desktop processors with up to 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module (MCM) is fabricated with the GlobalFoundries' 14 nm (14HP) process, while the Matisse's I/O die uses the GlobalFoundries' "12 nm" (12LP+) process. The Radeon RX 5000 series is also based on TSMC's N7 process.
7 nm scale MOSFETs were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6 nm silicon-on-insulator (SOI) MOSFET.[13][14] In 2003, NEC's research team led by Hitoshi Wakabayashi and Shigeharu Yamagami fabricated a 5 nm MOSFET.[15][16]
In July 2015, IBM announced that they had built the first functional transistors with "7 nm" technology, using a silicon-germanium process.[17][18][19][20]
In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their "7 nm" process,[2] with a cell area of 0.027 square micrometers (550 F2)[spelling?] with reasonable risk production yields.[21]
In 2015, Intel expected that at the 7nm node, III-V semiconductors would have to be used in transistors, signaling a shift away from silicon.[22]
In April 2016, TSMC announced that "7 nm" trial production would begin in the first half of 2017.[23] In April 2017, TSMC began risk production of 256 Mbit SRAM memory chips using a "7 nm" (N7FF+) process,[2] with extreme ultraviolet lithography (EUV).[24] TSMC's "7 nm" production plans, as of early 2017,[needs update] were to use deep ultraviolet (DUV) immersion lithography initially on this process node (N7FF), and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation "7 nm" (N7FF+) production was planned[needs update] to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.[25]
In September 2016, GlobalFoundries announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.[26]
In February 2017, Intel announced Fab 42 in Chandler, Arizona, which was according to press releases at that time expected[needs update] to produce microprocessors using a "7 nm" (Intel 4[27]) manufacturing process.[28] The company had not, at that time, published any expected values for feature lengths at this process node.[needs update]
In April 2018, TSMC announced volume production of "7 nm" (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.[3]
In May 2018, Samsung announced production of "7 nm" (7LPP) chips this year. ASML Holding NV is their main supplier of EUV lithography machines.[29]
In August 2018, GlobalFoundries announced it was stopping development of "7 nm" chips, citing cost.[30]
On October 28, 2018, Samsung announced their second generation "7 nm" process (7LPP) had entered risk production and was at that time expected to have entered mass production by 2019.[needs update]
On January 17, 2019, for the Q4 2018 earnings call, TSMC mentioned that different customers would have "different flavors" of second generation "7 nm".[31][needs update]
On April 16, 2019, TSMC announced their "6 nm" process called (CLN6FF, N6), which was, according to a press release made on April 16, 2019, at that time expected to have been in mass products from 2021.[32][needs update] N6 was at that time expected to have used EUVL in up to 5 layers, compared to up to 4 layers in their N7+ process.[33]
On July 28, 2019, TSMC announced their second gen "7 nm" process called N7P, which was projected to have been DUV-based like their N7 process.[34] Since N7P was fully IP-compatible with the original "7 nm", while N7+ (which uses EUV) was not, N7+ (announced earlier as "7 nm+") was to have been a separate process from "7 nm". N6 ("6 nm"), another EUV-based process, was at that time planned to have been released later than even TSMC's "5 nm" (N5) process, with the IP-compatibility with N7. At their Q1 2019 earnings call, TSMC reiterated their Q4 2018 statement[31] that N7+ was at that time expected to have generated less than $1 billion TWD in revenue in 2019.[35][needs update]
On October 5, 2019, AMD announced their EPYC Roadmap, featuring Milan chips built using TSMC's N7+ process.[36][needs update]
On October 7, 2019, TSMC announced they had started delivering N7+ products to market in high volume.[37][needs update]
On July 26, 2021, Intel announced their new manufacturing roadmap, renaming all of their future process nodes.[27] Intel's "10 nm" Enhanced SuperFin (10ESF), which was roughly equivalent to TSMC's N7 process, would thenceforth be known as "Intel 7", while their earlier "7 nm" process would erstwhile be called "Intel 4".[27][38] As a result, Intel's first processors based on Intel 7 were at that time planned to have started shipping by the second half of 2022,[needs update] whereas Intel announced earlier that they were planning to have launched "7 nm" processors in 2023.[39][needs update]
Technology commercialization
In June 2018, AMD announced 7 nm Radeon Instinct GPUs launching in the second half of 2018.[40] In August 2018, the company confirmed the release of the GPUs.[41]
On September 12, 2018, Apple announced their A12 Bionic chip used in iPhone XS and iPhone XR built using TSMC's 7 nm (N7) process. The A12 processor became the first 7 nm chip for mass market use as it released before the Huawei Mate 20.[42][43] On October 30, 2018, Apple announced their A12X Bionic chip used in iPad Pro built using TSMC's 7 nm (N7) process.[44]
On December 4, 2018, Qualcomm announced their Snapdragon855 and 8cx built using TSMC's 7 nm (N7) process.[45] The first mass product featuring the Snapdragon 855 was the Lenovo Z5 Pro GT, which was announced on December 18, 2018.[46]
On May 29, 2019, MediaTek announced their 5G SoC built using a TSMC 7 nm process.[47]
On July 7, 2019, AMD officially launched their Ryzen 3000 series of central processing units, based on the TSMC 7 nm process and Zen 2 microarchitecture.
On August 6, 2019, Samsung announced their Exynos 9825 SoC, the first chip built using their 7LPP process. The Exynos 9825 is the first mass market chip built featuring EUVL.[48]
7 nm (N7 nodes) manufacturing made up 36% of TSMC's revenue in the second quarter of 2020.[51]
On August 17, 2020, IBM announced their Power10 processor.[50]
On July 26, 2021, Intel announced that their Alder Lake processors would be manufactured using their newly rebranded "Intel 7" process, previously known as "10 nm Enhanced SuperFin".[27] These processors were, at that time, expected based on press releases to have been planned to have been released in the second half of 2021.[needs update] The company earlier confirmed a 7 nm, now called "Intel 4",[27] microprocessor family called Meteor Lake to be released in 2023.[52][53][needs update]
Patterning difficulties
Pitch splitting issues. Successive litho-etch patterning is subject to overlay errors as well as the CD errors from different exposures.Spacer patterning issues. Spacer patterning has excellent CD control for features directly patterned by the spacer, but the spaces between spacers may be split into core and gap populations.Overlay error impact on line cut. An overlay error on a cut hole exposure could distort the line ends (top) or infringe on an adjacent line (bottom).Two-bar EUV patterning issues. In EUV lithography, a pair of features may not have both features in focus at the same time; one will have different size from the other, and both will shift differently through focus as well.7 nm EUV stochastic failure probability. "7 nm" features were expected to approach ~20 nm width. The probability of EUV stochastic failure is measurably high for the commonly applied dose of 30 mJ/cm2.
The "7 nm" foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.
Pitch splitting
Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.
Spacer patterning
Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'.[54] Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation (e.g., fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.
When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.
Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.
Self-aligned litho-etch-litho-etch (SALELE) has been implemented for "7 nm" BEOL patterning.[55]
EUV lithography
Extreme ultraviolet lithography (also known as EUV or EUVL) is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus.[56][57][58] This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.[59]
EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures.[60][61] The defect level is on the order of 1K/mm2.[62]
The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint.[63] A separate exposure(s) for cutting lines is preferred.
Attenuated phase shift masks have been used in production for 90 nm node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength (193 nm),[64][65] whereas this resolution enhancement is not available for EUV.[66][67]
At 2021 SPIE's EUV Lithography conference, it was reported by a TSMC customer that EUV contact yield was comparable to immersion multipatterning yield.[68]
Comparison with previous nodes
Due to these challenges, "7 nm" poses unprecedented patterning difficulty in the back end of line (BEOL). The previous high-volume, long-lived foundry node (Samsung "10 nm", TSMC "16 nm") used pitch splitting for the tighter pitch metal layers.[69][70][71]
Single-patterned layer: 1 day completion by immersion
6000 wafers/day
1500 wafers/day
Double-patterned layer: 2 days completion by immersion
6000 wafers/2 days
3000 wafers/2 days
Triple-patterned layer: 3 days completion by immersion
6000 wafers/3 days
4500 wafers/3 days
Quad-patterned layer: 4 days completion by immersion
6000 wafers/4 days
6000 wafers/4 days
Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.
Design rule management in volume production
The "7 nm" metal patterning currently practiced by TSMC involves self-aligned double patterning (SADP) lines with cuts inserted within a cell on a separate mask as needed to reduce cell height.[74] However, self-aligned quad patterning (SAQP) is used to form the fin, the most important factor to performance.[75] Design rule checks also allow via multi-patterning to be avoided, and provide enough clearances for cuts that only one cut mask is needed.[75]
The naming of process nodes by 4 different manufacturers (TSMC, Samsung, SMIC, Intel) is partially marketing-driven and not directly related to any measurable distance on a chip – for example TSMC's "7 nm" node was previously similar in some key dimensions to Intel's planned first-iteration "10 nm" node, before Intel released further iterations, culminating in "10nm Enhanced SuperFin", which was later renamed to "Intel 7" for marketing reasons.[76][77]
Since EUV implementation at "7 nm" is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's "7 nm", even with EUV single-patterned 36 nm pitch layers, 44 nm pitch layers would still be quadruple patterned.[78]
April 2021 risk production, mass production unknown
Late 2021 risk production, quietly produced since July 2021[99]
Postponed due to US embargo
GlobalFoundries' "7 nm" 7LP (Leading Performance) process would have offered 40% higher performance or 60%+ lower power with a 2x scaling in density and at a 30-45+% lower cost per die over its "14 nm" process. The Contacted Poly Pitch (CPP) would have been 56 nm and the Minimum Metal Pitch (MMP) would have been 40 nm, produced with Self-Aligned Double Patterning (SADP). A 6T SRAM cell would have been 0.269 square microns in size. GlobalFoundries planned to eventually use EUV lithography in an improved process called 7LP+.[100] GlobalFoundries later stopped all "7 nm" and beyond process development.[101]
Intel's new "Intel 7" process, previously known as "10 nm Enhanced SuperFin" (10ESF), is based on its previous "10 nm" node. The node will feature a 10-15% increase in performance per watt. Meanwhile, their old "7 nm" process, now called "Intel 4", was at that time expected to have been released in 2023.[102][needs update] Few details about the "Intel 4" node had at that time been made public, although its transistor density had at that time been estimated to be at least 202 million transistors per square millimeter.[27][103][needs update] As of 2020, Intel had been experiencing problems with its "Intel 4" process to the point of outsourcing production of its Ponte Vecchio GPUs.[104][105][needs update]
^Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting. pp. 267–270. doi:10.1109/IEDM.2002.1175829. ISBN0-7803-7462-2. S2CID10151651.
^Jeong, W. C.; Ahn, J. H.; Bang, Y. S.; Yoon, Y. S.; Choi, J. Y.; Kim, Y. C.; Paek, S. W.; Ahn, S. W.; Kim, B. S.; Song, T. J.; Jung, J. H.; Do, J. H.; Lim, S. M.; Cho, H.-; Lee, J. H.; Kim, D. W.; Kang, S. B.; Ku, J.-; Kwon, S. D.; Jung, S.-; Yoon, J. S. (June 23, 2017). "10nm 2nd generation BEOL technology with optimized illumination and LELELELE". 2017 Symposium on VLSI Technology. pp. T144–T145. doi:10.23919/VLSIT.2017.7998156. ISBN978-4-86348-605-8. S2CID43207918 – via IEEE Xplore.
^Wu, S.; Lin, C. Y.; Chiang, M. C.; Liaw, J. J.; Cheng, J. Y.; Yang, S. H.; Liang, M.; Miyashita, T.; Tsai, C. H.; Hsu, B. C.; Chen, H. Y.; Yamamoto, T.; Chang, S. Y.; Chang, V. S.; Chang, C. H.; Chen, J. H.; Chen, H. F.; Ting, K. C.; Wu, Y. K.; Pan, K. H.; Tsui, R. F.; Yao, C. H.; Chang, P. R.; Lien, H. M.; Lee, T. L.; Lee, H. M.; Chang, W.; Chang, T.; Chen, R.; Yeh, M.; Chen, C. C.; Chiu, Y. H.; Chen, Y. H.; Huang, H. C.; Lu, Y. C.; Chang, C. W.; Tsai, M. H.; Liu, C. C.; Chen, K. S.; Kuo, C. C.; Lin, H. T.; Jang, S. M.; Ku, Y. (December 23, 2013). "A 16nm FinFET CMOS technology for mobile SoC and computing applications". 2013 IEEE International Electron Devices Meeting. pp. 9.1.1–9.1.4. doi:10.1109/IEDM.2013.6724591. ISBN978-1-4799-2306-9 – via IEEE Xplore.
