Beyond CMOS refers to the possible future digital logic technologies beyond the scaling limits of CMOS technology.[1][2][3][4] which limits device density and speeds due to heating effects.[5]

Beyond CMOS is the name of one of the 7 focus groups in ITRS 2.0 (2013) and in its successor, the International Roadmap for Devices and Systems.

CPU Clock Scaling

CPUs using CMOS were released from 1986 (e.g. 12 MHz Intel 80386). As CMOS transistor dimensions were shrunk the clock speeds also increased. Since about 2004 CMOS CPU clock speeds have leveled off at about 3.5 GHz.

A graph of efficiency gains possible under 'more Moore' (ie, further improvements to current technology) and 'Beyond CMOS' (ie, a paradigm shift in technology). From the International Roadmap for Devices and Systems[6]

CMOS devices sizes continue to shrink – see Intel tick–tock and ITRS:

It is not yet clear if CMOS transistors will still work below 3 nm.[4] See 3 nanometer.

Comparisons of technology

About 2010 the Nanoelectronic Research Initiative (NRI) studied various circuits in various technologies.[2]

Nikonov benchmarked (theoretically) many technologies in 2012,[2] and updated it in 2014.[8] The 2014 benchmarking included 11 electronic, 8 spintronic, 3 orbitronic, 2 ferroelectric, and 1 straintronics technology.[8]

The 2015 ITRS 2.0 report included a detailed chapter on Beyond CMOS,[9] covering RAM and logic gates.

Some areas of investigation

Superconducting computing and RSFQ

Superconducting computing includes several beyond-CMOS technologies that use superconducting devices, namely Josephson junctions, for electronic signals processing and computing. One variant called rapid single-flux quantum (RSFQ) logic was considered promising by the NSA in a 2005 technology survey despite the drawback that available superconductors require cryogenic temperatures. More energy-efficient superconducting logic variants have been developed since 2005 and are being considered for use in large scale computing.[12][13]

See also

References

  1. ^ "Extending the road beyond CMOS. Hutchby 2002" (PDF). Archived (PDF) from the original on 2022-12-06. Retrieved 2023-04-16.
  2. ^ a b c Nikonov, Dmitri E.; Young, Ian A. (September 2012). "Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking". arXiv:1302.0244 [cond-mat.mes-hall].
  3. ^ Bernstein; et al. (2011). "Device and Architecture Outlook for Beyond CMOS Switches". Archived from the original on 2015-02-22. Retrieved 2015-02-22. ((cite journal)): Cite journal requires |journal= (help)
  4. ^ a b "Review of Advanced and Beyond CMOS FET Technologies for Radio Frequency Circuit Design. Carta 2011" (PDF). Archived from the original (PDF) on 2015-02-23. Retrieved 2015-02-23.
  5. ^ Frank, D.J. (March 2002). "Power-constrained CMOS scaling limits". IBM Journal of Research and Development. 46 (2.3): 235–244. CiteSeerX 10.1.1.84.4043. doi:10.1147/rd.462.0235.
  6. ^ "Beyond CMOS" (PDF). The International Roadmap for Devices and Systems (2017 ed.). IEEE. 2018. Archived (PDF) from the original on 2018-07-03. Retrieved 2018-07-03.
  7. ^ "Samsung vows to start 10nm chip production in 2016". 23 May 2015. Archived from the original on 16 July 2015. Retrieved 16 July 2015.
  8. ^ a b Nikonov; Young (2015). "Benchmarking of Beyond-CMOS Exploratory – Devices for Logic Integrated Circuits". IEEE Journal on Exploratory Solid-State Computational Devices and Circuits. 1: 3–11. Bibcode:2015IJESS...1....3N. doi:10.1109/JXCDC.2015.2418033.
  9. ^ Beyond CMOS (PDF). International Technology Roadmap for Semiconductors 2.0 (2015 ed.). Archived (PDF) from the original on 2023-04-16. Retrieved 2017-06-16.
  10. ^ Manipatruni, Sasikanth; Nikonov, Dmitri E.; Lin, Chia-Ching; Gosavi, Tanay A.; Liu, Huichu; Prasad, Bhagwati; Huang, Yen-Lin; Bonturim, Everton; Ramesh, Ramamoorthy; Young, Ian A. (2018-12-03). "Scalable energy-efficient magnetoelectric spin–orbit logic". Nature. 565 (7737): 35–42. doi:10.1038/s41586-018-0770-2. ISSN 0028-0836. PMID 30510160. S2CID 256769872.
  11. ^ Seabaugh (September 2013). "The Tunneling Transistor". IEEE Spectrum. IEEE. 50 (10): 35–62. doi:10.1109/MSPEC.2013.6607013. S2CID 2729197. Archived from the original on 2021-06-29. Retrieved 2023-04-16.
  12. ^ Holmes, D.S.; Ripple, A.L.; Manheimer, M.A. (June 2013). "Energy-efficient superconducting computing—power budgets and requirements". IEEE Trans. Appl. Supercond. 23 (3). 1701610. Bibcode:2013ITAS...2301610H. doi:10.1109/TASC.2013.2244634. S2CID 20374012. Archived from the original on 2022-10-10. Retrieved 2023-04-16.
  13. ^ Holmes, D.S.; Kadin, A.M.; Johnson, M.W. (December 2015). "Superconducting Computing in Large-Scale Hybrid Systems". Computer. 48 (12): 34–42. doi:10.1109/MC.2015.375. S2CID 26578755. Archived from the original on 2022-12-25. Retrieved 2023-04-16.

Further reading

External links

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