In the electronics industry, dark silicon is the amount of circuitry of an integrated circuit that cannot be powered-on at the nominal operating voltage for a given thermal design power (TDP) constraint.

Dennard scaling would posit that as transistors get smaller, they become more efficient in proportion to the increase in number for a given area, but this scaling has broken down in recent years, meaning that increases in the efficiency of smaller transistors are not proportionate with the increase in their number. This discontinuation of scaling has led to sharp increases in power density that hamper powering-on all transistors simultaneously while keeping temperatures in a safe operating range.[1]

As of 2011, researchers from different groups have projected that, at 8 nm technology nodes, the amount of dark silicon may reach up to 50–80%[2] depending upon the processor architecture, cooling technology, and application workloads. Dark silicon may be unavoidable even in server workloads with abundance of inherent client request-level parallelism.[3]

Challenges and opportunities

The emergence of dark silicon introduces several challenges for the architecture, electronic design automation (EDA), and hardware-software co-design communities. These include the question of how best to utilize the plethora of transistors (with potentially many dark ones) when designing and managing energy-efficient on-chip many-core processors under peak power and thermal constraints. Architects have initiated several efforts to leverage dark silicon in designing application-specific and accelerator-rich architectures.[4][5][6]

Recently, researchers have explored how dark silicon exposes new challenges and opportunities for the EDA community.[7] In particular, they have demonstrated thermal, reliability (soft error and aging), and process variation concerns for dark silicon many-core processors.

References

  1. ^ Taylor, Michael B. (June 2012). "Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse". DAC Design Automation Conference 2012: 1131–1136.
  2. ^ Esmaeilzadeh, Hadi; et al. (June 2011). "Dark silicon and the end of multicore scaling" (PDF). 2011 38th Annual International Symposium on Computer Architecture (ISCA): 365–376.
  3. ^ Hardavellas, Nikos; Ferdman, Michael; Falsafi, Babak; Ailamaki, Anastasia (2011). "Toward Dark Silicon in Servers" (PDF). IEEE Micro. 31 (4): 6. doi:10.1109/MM.2011.77. ISSN 1937-4143. S2CID 2765349.
  4. ^ Venkatesh, Ganesh; Sampson, Jack; Goulding, Nathan; Garcia, Saturnino; Bryksin, Vladyslav; Lugo-Martinez, Jose; Swanson, Steven; Taylor, Michael Bedford (2010-03-13). "Conservation cores: reducing the energy of mature computations" (PDF). ACM SIGPLAN Notices. 45 (3): 205–218. doi:10.1145/1735971.1736044. ISSN 0362-1340.
  5. ^ Cong, Jason; Ghodrat, Mohammad Ali; Gill, Michael; Grigorian, Beayna; Reinman, Glenn (2012-06-03). "Architecture support for accelerator-rich CMPS". Proceedings of the 49th Annual Design Automation Conference. DAC '12. San Francisco, California: Association for Computing Machinery. pp. 843–849. doi:10.1145/2228360.2228512. ISBN 978-1-4503-1199-1. S2CID 15870762.
  6. ^ Lyons, Michael J.; Hempstead, Mark; Wei, Gu-Yeon; Brooks, David (2012-01-26). "The accelerator store: A shared memory framework for accelerator-based systems". ACM Transactions on Architecture and Code Optimization. 8 (4): 48:1–48:22. CiteSeerX 10.1.1.226.994. doi:10.1145/2086696.2086727. ISSN 1544-3566.
  7. ^ Shafique, Muhammad; Garg, Siddharth; Henkel, Jörg; Marculescu, Diana (2014-06-01). "The EDA Challenges in the Dark Silicon Era". Proceedings of the 51st Annual Design Automation Conference. DAC '14. San Francisco, CA, USA: Association for Computing Machinery. pp. 1–6. doi:10.1145/2593069.2593229. ISBN 978-1-4503-2730-5. S2CID 10686259.
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