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((Short description|Instruction slot being executed without the effects of a preceding instruction))
((more citations needed|date=October 2023))

In [[computer architecture]], a '''delay slot''' is an instruction slot being executed without the effects of a preceding instruction.<ref>((cite book  |title=Computer Archtecture A Quantitative Approach |last1=A.Patterson |first1=David |last2=L.Hennessy |first2=John |isbn=1-55860-069-8 |page=275 |year=1990 |date= |publisher=Morgan Kaufmann Publishers))</ref> The most common form is a single arbitrary instruction located immediately after a [[Branch (computer science)|branch]] [[instruction (computer science)|instruction]] on a [[RISC]] or [[Digital signal processor|DSP]] architecture; this instruction will execute even if the preceding branch is taken. Thus, by design, the instructions appear to execute in an illogical or incorrect order. It is typical for [[Assembly language|assembler]]s to automatically reorder instructions by default, hiding the awkwardness from assembly developers and compilers.((citation needed|date=June 2021))

==Branch delay slots==
When a branch instruction is involved, the location of the following delay slot instruction in the [[instruction pipeline|pipeline]] may be called a '''branch delay slot'''. Branch delay slots are found mainly in [[Digital signal processor|DSP]] architectures and older [[RISC]] architectures. [[MIPS architecture|MIPS]], [[PA-RISC]] (delayed or non-delayed branch can be specified),<ref>((Cite web |url=https://dl.acm.org/doi/pdf/10.1145/30350.30352 |first1=John A. |last1=DeRosa |first2=Henry M. |last2=Levy |title=An Evaluation of Branch Architectures |page=1 |accessdate=2024-01-27))</ref> [[ETRAX CRIS]], [[SuperH]] (unconditional branch instructions have one delay slot),<ref>((cite web |url=https://www.renesas.com/us/en/document/mah/superh-risc-engine-sh7020-and-sh7021-hd6437020-hd6477021-hd6437021-hd6417021?r=469371 |page=42,70 |title=SH7020 and SH7021 Hardware ManualSuperH™ RISC engine |accessdate=2023-12-17))</ref> [[Am29000]],<ref>((Cite web |url=https://ia902802.us.archive.org/22/items/29kprog/29kprog.pdf#page=78 |title=Evaluating and Programming the 29K RISC Family Third Edition – DRAFT |page=54 |accessdate=2023-12-20))</ref> [[Intel i860]] (unconditional branch instructions have one delay slot),<ref>((Cite web |url=http://www.bitsavers.org/components/intel/i860/240329-002_i860_64-Bit_Microprocessor_Programmers_Reference_Feb89.pdf#page=70 |title=i860™ 64-bit Microprocessor Programmer's Reference Manual |page=70(5-11) |accessdate=2023-12-21))</ref> [[MC88000]] (delayed or non-delayed branch can be specified),<ref>((Cite web |url=http://www.bitsavers.org/components/motorola/88000/MC88100_RISC_Microprocessor_Users_Manual_2ed_1990.pdf#page=81 |title=MC88100 RISC Microprocessor User's Manual |page=81(3-26) |accessdate=2023-12-21))</ref> and [[SPARC]] are RISC architectures that each have a single branch delay slot; [[PowerPC]], [[ARM architecture|ARM]], [[DEC Alpha|Alpha]], [[V850]], and [[RISC-V]] do not have any. [[Digital signal processor|DSP]] architectures that each have a single branch delay slot include [[NEC μPD77230|μPD77230]]<ref>((cite web |url=http://www.bitsavers.org/components/nec/_dataSheets/uPD77230_Advanced_Signal_Processor_198603.pdf |title=μPD77230 Advanced Signal Processor |accessdate=2023-11-05 |page=191(4-76)))</ref> and the [[VS DSP]]. The [[Super Harvard Architecture Single-Chip Computer|SHARC]] DSP and [[MIPS-X]] use a double branch delay slot;<ref>((cite web |url=https://apps.dtic.mil/sti/tr/pdf/ADA181619.pdf |title=MIPS-X Instruction Set and Programmer's Manual |page=18 |accessdate=2023-12-03))</ref> such a processor will execute a pair of instructions following a branch instruction before the branch takes effect. Both [[Texas Instruments TMS320|TMS320C3x]]<ref>((cite web |url=https://www.ti.com/lit/an/spra397/spra397.pdf#page=14 |title=The TMS320C30 Floating-Point Digital Signal Processor |accessdate=2023-11-04 |publisher=ti.com |page=14 ))</ref> and [[Texas Instruments TMS320|TMS320C4x]]<ref name="tms320c4x-bra">((cite web |url=https://www.ti.com/lit/ug/spru063c/spru063c.pdf#page=171 |title=TMS320C4x User's Guide |accessdate=2023-10-29 |page=171(7-9)))</ref> use a triple branch delay slot. The TMS320C4x has both non-delayed and delayed branches.<ref name="tms320c4x-bra"/>

The following example shows delayed branches in assembly language for the SHARC DSP including a pair after the RTS instruction. Registers R0 through R9 are cleared to zero in order by number (the register cleared after R6 is R7, not R9). No instruction executes more than once.
<pre>
     R0 = 0;
     CALL fn (DB);      /* call a function, below at label "fn" */
     R1 = 0;            /* first delay slot */
     R2 = 0;            /* second delay slot */
     /***** discontinuity here (the CALL takes effect) *****/

     R6 = 0;            /* the CALL/RTS comes back here, not at "R1 = 0" */
     JUMP end (DB);
     R7 = 0;            /* first delay slot */
     R8 = 0;            /* second delay slot */
     /***** discontinuity here (the JUMP takes effect) *****/

     /* next 4 instructions are called from above, as function "fn" */
fn:  R3 = 0;
     RTS (DB);          /* return to caller, past the caller's delay slots */
     R4 = 0;            /* first delay slot */
     R5 = 0;            /* second delay slot */
     /***** discontinuity here (the RTS takes effect) *****/

end: R9 = 0;
</pre>

The goal of a [[Classic RISC pipeline|pipelined architecture]] is to complete an instruction every clock cycle. To maintain this rate, the pipeline must be full of instructions at all times. The branch delay slot is a side effect of pipelined architectures due to the [[Hazard (computer architecture)|branch hazard]], i.e. the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the [[program counter]]. Each cycle where a stall is inserted is considered one branch delay slot. A more sophisticated design would execute program instructions that are not dependent on the result of the branch instruction. This optimization can be performed in [[software]] at [[compile time]] by moving instructions into branch delay slots in the in-memory instruction stream, if the hardware supports this. Another side effect is that special handling is needed when managing [[breakpoint]]s on instructions as well as stepping while [[debugging]] within branch delay slot. An interrupt is unable to occur during a branch delay slot and is deferred until after the branch delay slot.<ref>((cite web |url=http://www.bitsavers.org/components/nec/_dataSheets/uPD77230_Advanced_Signal_Processor_198603.pdf |title=μPD77230 Advanced Signal Processor |pages=38(3-39), 70(3-41) |accessdate=2023-11-17 ))</ref><ref>((cite web |url=https://www.ti.com/lit/ug/spru063c/spru063c.pdf#page=171 |title=TMS320C4x User's Guide |accessdate=2023-12-02 |page=75(3-15)))</ref>  Placing branch instruction in the branch delay slot is prohibited or deprecated.<ref>((cite web |url=http://www.bitsavers.org/components/nec/_dataSheets/uPD77230_Advanced_Signal_Processor_198603.pdf#page=191 |title=μPD77230 Advanced Signal Processor |accessdate=2023-10-28 |page=191(4-76)))</ref><ref name="tms320c4x-bra"/><ref>((Cite web |url=http://www.bitsavers.org/components/motorola/88000/MC88100_RISC_Microprocessor_Users_Manual_2ed_1990.pdf#page=88 |title=MC88100 RISC Microprocessor User's Manual |page=88(3-33) |accessdate=2023-12-30))</ref>

The ideal number of branch delay slots in a particular pipeline implementation is dictated by the number of pipeline stages, the presence of [[Hazard (computer architecture)#Register forwarding|register forwarding]], what stage of the pipeline the branch conditions are computed, whether or not a [[branch target buffer]] (BTB) is used and many other factors. Software compatibility requirements dictate that an architecture may not change the number of delay slots from one generation to the next. This inevitably requires that newer hardware implementations contain extra hardware to ensure that the architectural behavior is followed despite no longer being relevant.

==Load delay slot==
A load delay slot is an instruction which executes immediately after a load (of a register from memory) but does not see, and need not wait for, the result of the load. Load delay slots are very uncommon because load delays are highly unpredictable on modern hardware. A load may be satisfied from RAM or from a cache, and may be slowed by resource contention. Load delays were seen on very early RISC processor designs. The [[MIPS I]] ISA (implemented in the [[R2000 (microprocessor)|R2000]] and [[R3000]] microprocessors) suffers from this problem.

The following example is MIPS I assembly code, showing both a load delay slot and a branch delay slot.
<syntaxhighlight lang="asm">
   lw   v0,4(v1)   # load word from address v1+4 into v0
   nop             # wasted load delay slot
   jr   v0         # jump to the address specified by v0
   nop             # wasted branch delay slot
</syntaxhighlight>

== See also ==
*[[Control flow]]
*[[Bubble (computing)]]
*[[Branch predication]]

== References ==
((reflist))

== External links ==
((refbegin))
*((cite book |first1=J.A. |last1=DeRosa |first2=H.M. |last2=Levy |chapter=An evaluation of branch architectures §2 Delayed Branches |chapter-url=https://dl.acm.org/doi/pdf/10.1145/30350.30352 |title=Proceedings of the 14th annual international symposium on Computer architecture (ISCA '87) |publisher=Association for Computing Machinery |date=1987 |isbn=978-0-8186-0776-9 |pages=10–16 |doi=10.1145/30350.30352|s2cid=1870852 ))
*((cite web |title=Branch Prediction Schemes |url=http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/branchPred.html |work=Computer Architecture Tutorial |date= |first=Gurpur M. |last=Prabhu |publisher=Iowa State University|archive-url=https://web.archive.org/web/20200807053823/http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/branchPred.html |archive-date=2020-08-07 ))
((refend))

[[Category:Instruction processing]]

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