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((more citations needed|date=October 2013))

In [[VHDL]] [[Simulation software|simulation]]s, all [[Assignment (computer science)|assignments]] to ''signals'' (a VHDL concept that represents a [[Netlist|net]] connecting different components together) occur with some infinitesimal [[Latency (engineering)|delay]], known as '''delta delay''', unless a delay is specified.<ref>((cite book|last=Bhasker|first=Jayaram|title=A Vhdl Primer|year=1999|publisher=Prentice Hall PTR, 1999|isbn=9780130965752|pages=31, 46))</ref>  Technically, delta delay is of no [[Measure (mathematics)|measurable]] [[Units of measurement|unit]], but from a [[digital electronics]] hardware design perspective one should think of delta delay as being the smallest [[Unit of time|time unit]] one could measure, such as a [[femtosecond]] (fs).

==References==
((Reflist))

((DEFAULTSORT:Delta Delay))
[[Category:Hardware description languages]]


((simulation-software-stub))

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