Domino logic is a CMOS-based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing. It was developed to speed up circuits, solving the premature cascade problem, typically by inserting small and fast pFETs between domino stages to constrain the interstage cascade velocity to a curtailed maximum—a curtailed deterministic maximum—without requiring other circuit design interlocks.
The term derives from the fact that in domino logic (cascade structure consisting of several stages), each stage ripples the next stage for evaluation, similar to dominoes falling one after the other.
In dynamic logic, a problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.
In order to cascade dynamic logic gates, one solution is domino logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a pFET (one of the main goals of dynamic logic is to avoid pFETs where possible, due to speed), there are two reasons it works well. First, there is no fan-out to multiple pFETs; the dynamic gate connects to exactly one inverter, so the gate is still very fast. Furthermore, since the inverter connects to only nFETs in dynamic logic gates, it too is very fast. Second, the pFET in an inverter can be made smaller than in some types of logic gates.
In domino logic cascade structure of several stages, the evaluation of each stage ripples the next stage evaluation, similar to dominoes falling one after the other. Once fallen, the node states cannot return to "1" (until the next clock cycle) just as dominoes, once fallen, cannot stand up, justifying the name domino CMOS logic. It contrasts with other solutions to the cascade problem in which cascading is interrupted by clocks or other means.