Dry etching refers to the removal of material, typically a masked pattern of semiconductor material, by exposing the material to a bombardment of ions (usually a plasma of reactive gases such as fluorocarbons, oxygen, chlorine, boron trichloride; sometimes with addition of nitrogen, argon, helium and other gases) that dislodge portions of the material from the exposed surface. A common type of dry etching is reactive-ion etching. Unlike with many (but not all, see isotropic etching) of the wet chemical etchants used in wet etching, the dry etching process typically etches directionally or anisotropically.
Dry etching is used in conjunction with photolithographic techniques to attack certain areas of a semiconductor surface in order to form recesses in material.
Applications include contact holes (which are contacts to the underlying semiconductor substrate), via holes (which are holes that are formed to provide an interconnect path between conductive layers in the layered semiconductor device), transistor gates for FinFET technology, or to otherwise remove portions of semiconductor layers where predominantly vertical sides are desired. Along with semiconductor manufacturing, micromachining and display production, the removal of organic residues by oxygen plasmas is sometimes correctly described as a dry etch process. The term plasma ashing can be used instead.
Dry etching is particularly useful for materials and semiconductors which are chemically resistant and could not be wet etched, such as silicon carbide or gallium nitride.
Low density plasma (LDP) is able to produce high energy reactions at a low energy cost in thanks to its low pressure, meaning dry etch requires a relatively small quantity of chemicals and electricity to function. Additionally, dry etch equipment tends to be an order of magnitude cheaper than photolithography equipment, so many manufacturers rely on dry etching strategies such as pitch doubling or quartering to gain advanced resolutions (14nm+) while needing less advanced photolithography tools.
| Wet Etching | Dry Etching |
|---|---|
| highly selective | easy to start and stop |
| no damage to substrate | less sensitive to small changes in temperature |
| cheaper | more repeatable |
| slower | faster |
| may have anisotropies | |
| fewer particles in environment |
Dry etching is currently used in semiconductor fabrication processes due to its unique ability over wet etch to do anisotropic etching (removal of material) to create high aspect ratio structures (e.g. deep holes or capacitor trenches).
The dry etching hardware design basically involves a vacuum chamber, special gas delivery system, radio frequency (RF) waveform generator to supply power to the plasma, heated chuck to seat the wafer, and an exhaust system.
Design varies from manufacturers such as Tokyo Electronic, Applied Materials, and Lam. While all designs follow the same physical principles, the variety of designs target more specialized processing characteristics. For example, dry etch steps that come into contact with or form critical parts of the device may require higher levels of directionality, selectivity, and uniformity. The tradeoff is that more complex dry etch equipment comes at a higher cost to purchase and is more difficult to understand, more expensive to maintain, and may operate more slowly.
Dry etch equipment can control for process uniformity with several knobs. The chuck temperature can be varied to control the heat of the wafer across the radius of the wafer, which influences the rate of reactions and thus the etch rate across different regions of the wafer. The plasma uniformity can be controlled with plasma confinement, which may be controlled with a high speed magnet rotating around the chamber, variations in gas flow into the chamber and pump out of the chamber, or RF braiding around the chamber. These strategies vary per equipment manufacturer and intended application.
Dry etching process was invented by Stephen M. Irving who also invented the plasma etching process.[1][2] The anisotropic dry etching process was developed by Hwa-Nien Yu at the IBM T.J. Watson Research Center in the early 1970s. It was used by Yu with Robert H. Dennard to fabricate the first micron-scale MOSFETs (metal–oxide–semiconductor field-effect transistors) in the 1970s.[3]