In integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances.[1] It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics[citation needed], particularly central processing units (CPUs). Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design. Dynamic logic has a higher average rate of voltage transitions than static logic,[2] but the capacitive loads being transitioned are smaller[3] so the overall power consumption of dynamic logic may be higher or lower depending on various tradeoffs. When referring to a particular logic family, the dynamic adjective usually suffices to distinguish the design methodology, e.g. dynamic CMOS[4] or dynamic SOI design.[2]
Besides its use of dynamic state storage via voltages on capacitances, dynamic logic is distinguished from so-called static logic in that dynamic logic uses a clock signal in its implementation of combinational logic. The usual use of a clock signal is to synchronize transitions in sequential logic circuits. For most implementations of combinational logic, a clock signal is not even needed. The static/dynamic terminology used to refer to combinatorial circuits is related to the use of the same adjectives used to distinguish memory devices, e.g. static RAM from dynamic RAM, in that dynamic RAM stores state dynamically as voltages on capacitances, which must be periodically refreshed. But there are also differences in usage; the clock can be stopped in the appropriate phase in a system with dynamic logic and static storage.[5]
The largest difference between static and dynamic logic is that in dynamic logic, a clock signal is used to evaluate combinational logic. In most types of logic design, termed static logic, there is always some mechanism to drive the output either high or low. In many of the popular logic styles, such as TTL and traditional CMOS, this principle can be rephrased as a statement that there is always a low-impedance DC path between the output and either the supply voltage or the ground. As a side note, there is, of course, an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.
In contrast, in dynamic logic, there is not always a mechanism driving the output high or low. In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle. During the time intervals when the output is not being actively driven, stray capacitance causes it to maintain a level within some tolerance range of the driven level.
Dynamic logic requires a minimum clock rate fast enough that the output state of each dynamic gate is used or refreshed before the charge in the output capacitance leaks out enough to cause the digital state of the output to change, during the part of the clock cycle that the output is not being actively driven.
Static logic has no minimum clock rate—the clock can be paused indefinitely. While it may seem that doing nothing for long periods of time is not particularly useful, it leads to three advantages:
Being able to pause a system at any time for any duration can also be used to synchronize the CPU to an asynchronous event. While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins (for example, RDY on the 6502), or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting. In a basic design, to start waiting, the CPU would write to a register to set a binary latch bit which would be ANDed or ORed with the processor clock, stopping the processor. A signal from a peripheral device would reset this latch, resuming CPU operation. The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.
In particular, although many popular CPUs use dynamic logic,[citation needed] only static cores—CPUs designed with fully static technology—are usable in space satellites owing to their higher radiation hardness.[7][better source needed]
When properly designed, dynamic logic can be over twice as fast as static logic. It uses only the faster NMOS transistors, which improves transistor sizing optimizations. Static logic is slower because it has twice the capacitive loading, higher thresholds, and uses slow PMOS transistors for logic. Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed. Most electronics running at over 2 GHz these days[when?] require dynamic logic, although some manufacturers such as Intel have designed chips using completely static logic to reduce power consumption.[8] Note that reducing power use not only extends the running time with limited power sources such as batteries or solar arrays (as in spacecraft), but it also reduces the thermal design requirements, reducing the size of needed heatsinks, fans, etc., which in turn reduces system weight and cost.
In general, dynamic logic greatly increases the number of transistors that are switching at any given time, which increases power consumption over static CMOS.[8] There are several powersaving techniques that can be implemented in a dynamic logic based system. In addition, each rail can convey an arbitrary number of bits, and there are no power-wasting glitches. Power-saving clock gating and asynchronous techniques are much more natural in dynamic logic.
As an example, consider the static logic implementation of a CMOS NAND gate:
This circuit implements the logic function
If A and B are both high, the output will be pulled low. If either A or B are low, the output will be pulled high. At all times, the output is pulled either low or high.
Consider now a dynamic logic implementation of the same logic function:
The dynamic logic circuit requires two phases. The first phase, when Clock is low, is called the setup phase or the precharge phase, and the second phase, when Clock is high, is called the evaluation phase. In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B). The capacitor, which represents the load capacitance of this gate, becomes charged. Because the transistor at the bottom is turned off, it is impossible for the output to be driven low during this phase.
During the evaluation phase, Clock is high. If A and B are also high, the output will be pulled low. Otherwise, the output stays high (due to the load capacitance).
Dynamic logic has a few potential problems that static logic does not. For example, if the clock speed is too slow, the output will decay too quickly to be of use. Also, the output is only valid for part of each clock cycle, so the device connected to it must sample it synchronously when it is valid.
Also, when both A and B are high, so that the output is low, the circuit will pump one capacitor load of charge from Vdd to ground for each clock cycle, by first charging and then discharging the capacitor in each clock cycle. This makes the circuit (with its output connected to a high impedance) less efficient than the static version (which theoretically should not allow any current to flow except through the output), and when the A and B inputs are constant and both high, the dynamic NAND gate uses power in proportion to the clock rate, as long as it functions correctly. The power dissipation can be minimized by keeping the load capacitance low. This, in turn, reduces the maximum cycle time, requiring a higher minimum clock frequency; the higher frequency then increases power consumption by the relation mentioned. Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit derived from an equilibrium between clock speed and load capacitance.
A popular implementation is domino logic.
