The Wikibook Serial Programming:USB Technical Manual has a page on the topic of: USB connectors
The eXtensible Host Controller Interface (xHCI) is a technical specification that provides a detailed framework for the functioning of a computer's host controller for Universal Serial Bus (USB). Known alternately as the USB 3.0 host controller specification, xHCI is designed to be backward compatible, supporting a wide range of USB devices from older USB 1.x to the more recent USB 3.x versions.
Distinct from its predecessors, the Open Host Controller Interface (OHCI) and the Universal Host Controller Interface (UHCI), xHCI offers several technological improvements. Specifically, it is designed to handle multiple data transfer speeds (low, full, high, and SuperSpeed) within a single unified standard. This makes it more efficient in managing computational and power resources, a feature particularly beneficial for mobile devices with limited power capabilities like tablets and smartphones. Additionally, xHCI simplifies the architecture needed to support a mixture of low-speed and high-speed devices, which streamlines the development of drivers and system software.
xHCI marks a significant improvement over its predecessors, the Open Host Controller Interface (OHCI) and the Universal Host Controller Interface (UHCI), in several key ways:
By enhancing support for multiple speeds, optimizing power management, and simplifying the underlying architecture, xHCI serves as a more efficient and unified standard for USB host controllers.
The xHCI is a radical break from the previous generations of USB host controller interface architectures (i.e. the Open Host Controller Interface (OHCI), the Universal Host Controller Interface (UHCI), and the Enhanced Host Controller Interface (EHCI)) on many counts. Following are the key goals of the xHCI architecture:
The OHCI and UHCI controllers support only USB 1 speed devices (1.5 Mbit/s and 12 Mbit/s), and the EHCI only supports USB 2 devices (480 Mbit/s).
The xHCI architecture was designed to support all USB speeds, including SuperSpeed (5 Gbit/s) and future speeds, under a single driver stack.
When USB was originally developed in 1995, it was targeted at desktop platforms to stem the proliferation of connectors that were appearing on PCs, e.g. PS/2, serial port, parallel port, game port, etc., and host power consumption was not an important consideration at the time. Since then, mobile platforms have become the platform of choice, and their batteries have made power consumption a key consideration. The architectures of the legacy USB host controllers (OHCI, UHCI, and EHCI) were very similar in that the "schedule" for the transactions to be performed on the USB were built by software in host memory, and the host controller hardware would continuously read the schedules to determine what transactions needed to be driven on the USB, and when, even if no data was moved. Additionally, in the case of reads from the device, the device was polled each schedule interval, even if there was no data to read.
Legacy USB host-controller architectures exhibit some serious shortcomings when applied to virtualized environments. Legacy USB host-controller interfaces define a relatively simple hardware data-pump; where critical state related to overall bus-management (bandwidth allocation, address assignment, etc.) resides in the software of the host-controller driver (HCD). Trying to apply the standard hardware IO virtualization technique - replicating I/O interface registers - to the legacy USB host controller interface is problematic because critical state that must be managed across virtual machines (VMs) is not available to hardware. The xHCI architecture moves the control of this critical state into hardware, enabling USB resource management across VMs. The xHCI virtualization features also provide for:
The EHCI utilizes OHCI or UHCI controllers as "companion controllers", where USB 2 devices are managed through the EHCI stack, and the port logic of the EHCI allows a low-speed or full-speed USB device to be routed to a port of a "companion" UHCI or OHCI controller, where the low-speed or full-speed USB devices are managed through the respective UHCI or OHCI stack. For example, a USB 2 PCIe host controller card that presents 4 USB "Standard A" connectors typically presents one 4-port EHCI and two 2-port OHCI controllers to system software. When a high-speed USB device is attached to any of the 4 connectors, the device is managed through one of the 4 root hub ports of the EHCI controller. If a low-speed or full-speed USB device is attached to connectors 1 or 2, it will be routed to the root hub ports of one of the OHCI controllers for management, and low-speed and full-speed USB devices attached to connectors 3 or 4 will be routed to the root hub ports of the other OHCI controller. The EHCI dependence on separate host controllers for high-speed USB devices and the group of low-speed and full-speed USB devices results in complex interactions and dependencies between the EHCI and OHCI/UHCI drivers.
Support for Streams was added to the USB 3.0 SuperSpeed specification, primarily to enable high performance storage operations over USB. Classically there has been a 1:1 relationship between a USB endpoint and a buffer in system memory, and the host controller solely responsible for directing all data transfers. Streams changed this paradigm by providing a 1-to-many "endpoint to buffer" association, and allowing the device to direct the host controller as to which buffer to move. The USB data transfers associated with a USB Stream endpoint are scheduled by the xHCI the same as any other bulk endpoint is, however the data buffer associated with a transfer is determined by the device.
The xHCI architecture was designed to be highly scalable, capable of supporting 1 to 255 USB devices and 1 to 255 root hub ports. Since each USB device is allowed to define up to 31 endpoints, an xHCI that supported 255 devices would have to support 7,906 separate total endpoints. Classically, each memory buffer associated with an endpoint is described by a queue of physical memory blocks, where the queue requires a head pointer, tail pointer, length and other registers to define its state. There are many ways to define queue state, however if one were to assume 32 bytes of register space for each queue, then almost a 256KB of register space would be required to support 7,906 queues. Typically only a small number of USB devices are attached to a system at one time, and on the average a USB device supports 3-4 endpoints, of which only a subset of the endpoints are active at the same time. The xHCI maintains queue state in system memory as Endpoint Context data structures. The contexts are designed so that they can be cached by the xHCI, and "paged" in and out as a function of endpoint activity. Thus a vendor can scale their internal xHCI Endpoint Context cache space and resources to match the practical usage models expected for their products, rather than the architectural limits that they support. Ideally the internal cache space is selected so that under normal usage conditions, there is no context paging by the xHCI. Also USB endpoint activity tends to be bursty. That is, at any point in time a large number of endpoints may be ready to move data, however only a subset are actively moving data. For instance, the interrupt IN endpoint of a mouse may not transfer data for hours if the user is away from their desk. xHCI vendor specific algorithms could detect this condition and make that endpoint a candidate for paging out if other endpoints become busy.
The Open Host Controller Interface (OHCI) specification was defined by a consortium of companies (Compaq, Microsoft, and National Semiconductor) as open specification to support USB 1.0 devices. The Universal Host Controller Interface (UHCI) refers to a specification that Intel originally defined as a proprietary interface to support USB 1.0 devices. The UHCI specification was eventually made public, but only after the rest of industry had adopted the OHCI specification.
The EHCI specification was defined by Intel to support USB 2.0 devices. The EHCI architecture was modeled after the UHCI and OHCI controllers, which required software to build the USB transaction schedules in memory, and to manage bandwidth and address allocation. To eliminate a redundant industry effort of defining an open version of a USB 2.0 host controller interface, Intel made the EHCI specification available to the industry with no licensing fees.
The EHCI licensing model was continued for Intel's xHCI specification, however with a greatly expanded industry contribution. Over 100 companies have contributed to the xHCI specification. The USB Implementers Forum (USB-IF) has also funded a set of xHCI Compliance Tests to maximize the compatibility of the various xHCI implementations.
xHCI 1.0 controllers have been shipping since December 2009. Linux kernels since 2009 contain xHCI drivers,[4] but for older kernels there are drivers available online. Windows drivers for XP, Vista, and Windows 7 are available from the respective xHCI vendors. xHCI drivers for embedded system are available from MCCI, Jungo, and other software vendors. xHCI IP blocks are also available from several vendors for customization in SOC environments. xHCI 1.1 controllers and devices began shipping in 2015.
The xHCI specification uses "errata" files to define updates and clarifications to a specific release. The changes in the errata files are accumulated in each release. Refer to the associated errata files for the details of specific changes. Most changes defined in the xHCI errata files are clarifications, grammatical or spelling corrections, additional cross-references, etc., which do not affect a driver implementation. Changes that are determined to be architectural utilize a Capability flag to determine whether a particular feature is supported by an xHCI implementation, and an Enable flag to turn on the feature.
The xHCI specification evolved through several versions before its official release in 2010: