Fault grading is a procedure that rates testability by relating the number of fabrication defects that can in fact be detected with a test vector set under consideration to the total number of conceivable faults.

It is used for refining both the test circuitry and the test patterns iteratively, until a satisfactory fault coverage is obtained.[1]

See also

References

  1. ^ Kaeslin, Hubert (2008-04-28), Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Cambridge University Press, p. 24, ISBN 9780521882675
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