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Flat memory model or linear memory model refers to a memory addressing paradigm in which "memory appears to the program as a single contiguous address space."[1] The CPU can directly (and linearly) address all of the available memory locations without having to resort to any sort of memory segmentation or paging schemes.

Memory management and address translation can still be implemented on top of a flat memory model in order to facilitate the operating system's functionality, resource protection, multitasking or to increase the memory capacity beyond the limits imposed by the processor's physical address space, but the key feature of a flat memory model is that the entire memory space is linear, sequential and contiguous.

In a simple controller, or in a single tasking embedded application, where memory management is not needed nor desirable, the flat memory model is the most appropriate, because it provides the simplest interface from the programmer's point of view, with direct access to all memory locations and minimum design complexity.

In a general purpose computer system, which requires multitasking, resource allocation, and protection, the flat memory system must be augmented by some memory management scheme, which is typically implemented through a combination of dedicated hardware (inside or outside the CPU) and software built into the operating system. The flat memory model (at the physical addressing level) still provides the greatest flexibility for implementing this type of memory management.

The majority of processor architectures implement a flat memory design, including all early 8-bit processors, the Motorola 68000 series, etc. One exception was the original 8086, Intel's first 16-bit microprocessor, which implemented a crude segmented memory model which allowed access to more than 64 KiB of memory without the cost of extending all addresses to more than 16-bits.

Memory models

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Main article: Memory model

Most modern memory models fall into one of three categories:

Flat memory model

Paged memory model

Main article: Paging

X86 segmented memory model

Main articles: Memory segmentation and Intel Memory Model

Within the x86 architectures, when operating in the real mode (or emulation), physical address is computed as:[2]

Address = 16 × segment + offset

(I.e., the 16-bit segment register is shifted left by 4 bits and added to a 16-bit offset, resulting in a 20-bit address.)

See also


  1. ^ Gonzalez, Antonio; Latorre, Fernando; Magklis, Grigorios (2011). Processor Microarchitecture: An Implementation Perspective. Morgan & Claypool Publishers. p. 72. ISBN 9781608454525.
  2. ^ General description of Real Mode "The physical address can be calculated as Value_in_segment_register
    • 16 + Value_in_offset_register."