|Designed by||Computer Terminal Corporation (CTC)|
|Max. CPU clock rate||200 kHz to 800 kHz|
|Data width||8 bits|
|Address width||14 bits|
|Architecture and classification|
|Application||Computer terminals, calculators, bottling machines, 1970s ASEA industrial robots (IRB 6), simple computers, etc.|
|Technology node||10 µm|
The Intel 8008 ("eight-thousand-eight" or "eighty-oh-eight") is an early byte-oriented microprocessor designed by Computer Terminal Corporation (CTC), implemented and manufactured by Intel, and introduced in April 1972. It is an 8-bit CPU with an external 14-bit address bus that could address 16 KB of memory. Originally known as the 1201, the chip was commissioned by Computer Terminal Corporation (CTC) to implement an instruction set of their design for their Datapoint 2200 programmable terminal. As the chip was delayed and did not meet CTC's performance goals, the 2200 ended up using CTC's own TTL-based CPU instead. An agreement permitted Intel to market the chip to other customers after Seiko expressed an interest in using it for a calculator.
CTC formed in San Antonio in 1968 under the direction of Austin O. "Gus" Roche and Phil Ray, both NASA engineers. Roche, in particular, was primarily interested in producing a desktop computer. However, given the immaturity of the market, the company's business plan mentioned only a Teletype Model 33 ASR replacement, which shipped as the Datapoint 3300. The case was deliberately designed to fit in the same space as an IBM Selectric typewriter and used a video screen shaped to have the same aspect ratio as an IBM punched card. Although commercially successful, the 3300 had ongoing heat problems due to the amount of circuitry packed into such a small space.
In order to address the heating and other issues, a re-design started that featured the CPU part of the internal circuitry re-implemented on a single chip. Looking for a company able to produce their chip design, Roche turned to Intel, then primarily a vendor of memory chips. Roche met with Bob Noyce, who expressed concern with the concept; John Frassanito recalls that "Noyce said it was an intriguing idea, and that Intel could do it, but it would be a dumb move. He said that if you have a computer chip, you can only sell one chip per computer, while with memory, you can sell hundreds of chips per computer." Another major concern was that Intel's existing customer base purchased their memory chips for use with their own processor designs; if Intel introduced their own processor, they might be seen as a competitor, and their customers might look elsewhere for memory. Nevertheless, Noyce agreed to a $50,000 development contract in early 1970. Texas Instruments (TI) was also brought in as a second supplier.
TI was able to make samples of the 1201 based on Intel drawings, but these proved to be buggy and were rejected. Intel's own versions were delayed. CTC decided to re-implement the new version of the terminal using discrete TTL instead of waiting for a single-chip CPU. The new system was released as the Datapoint 2200 in the spring 1970, with their first sale to General Mills on May 25, 1970. CTC paused development of the 1201 after the 2200 was released, as it was no longer needed. Six months later, Seiko approached Intel, expressing an interest in using the 1201 in a scientific calculator, likely after seeing the success of the simpler Intel 4004 used by Busicom in their business calculators. A small re-design followed, under the leadership of Federico Faggin, the designer of the 4004, now project leader of the 1201, expanding from a 16-pin to 18-pin design, and the new 1201 was delivered to CTC in late 1971.
By that point, CTC had once again moved on, this time to the Datapoint 2200 II, which was faster. The 1201 was no longer powerful enough for the new model. CTC voted to end their involvement with the 1201, leaving the design's intellectual property to Intel instead of paying the $50,000 contract. Intel renamed it the 8008 and put it in their catalog in April 1972 priced at $120. This renaming tried to ride off the success of the 4004 chip, by presenting the 8008 as simply a 4 to 8 port, but the 8008 is not based on the 4004.  The 8008 went on to be a commercially successful design. This was followed by the Intel 8080, and then the hugely successful Intel x86 family.
One of the first teams to build a complete system around the 8008 was Bill Pentz' team at California State University, Sacramento. The Sac State 8008 was possibly the first true microcomputer, with a disk operating system built with IBM Basic assembly language in PROM, all driving a color display, hard drive, keyboard, modem, audio/paper tape reader and printer. The project started in the spring of 1972, and with key help from Tektronix the system was fully functional a year later. Bill assisted Intel with the MCS-8 kit and provided key input to the Intel 8080 instruction set, which helped make it useful for the industry and hobbyists.
In the UK, a team at S. E. Laboratories Engineering (EMI) led by Tom Spink in 1972 built a microcomputer based on a pre-release sample of the 8008. Joe Hardman extended the chip with an external stack. This, among other things, gave it power-fail save and recovery. Joe also developed a direct screen printer. The operating system was written using a meta-assembler developed by L. Crawford and J. Parnell for a Digital Equipment Corporation PDP-11. The operating system was burnt into a PROM. It was interrupt-driven, queued, and based on a fixed page size for programs and data. An operational prototype was prepared for management, who decided not to continue with the project.
The 8008 was the CPU for the very first commercial non-calculator personal computers (excluding the Datapoint 2200 itself): the US SCELBI kit and the pre-built French Micral N and Canadian MCM/70. It was also the controlling microprocessor for the first several models in Hewlett-Packard's 2640 family of computer terminals.
Intel offered an instruction set simulator for the 8008 named INTERP/8. It was written in FORTRAN.
|H||H register (indirect)|
|L||L register (indirect)|
|Push-down address call stack|
|AS||Call level 1|
|AS||Call level 2|
|AS||Call level 3|
|AS||Call level 4|
|AS||Call level 5|
|AS||Call level 6|
|AS||Call level 7|
The 8008 was implemented in 10 μm silicon-gate enhancement-mode PMOS logic. Initial versions could work at clock frequencies up to 0.5 MHz. This was later increased in the 8008-1 to a specified maximum of 0.8 MHz. Instructions take between 5 and 11 T-states, where each T-state is 2 clock cycles. Register–register loads and ALU operations take 5T (20 μs at 0.5 MHz), register–memory 8T (32 μs), while calls and jumps (when taken) take 11 T-states (44 μs). The 8008 is a little slower in terms of instructions per second (36,000 to 80,000 at 0.8 MHz) than the 4-bit Intel 4004 and Intel 4040. but since the 8008 processes data 8 bits at a time and can access significantly more RAM, in most applications it has a significant speed advantage over these processors. The 8008 has 3,500 transistors.
The chip, limited by its 18-pin DIP, has a single 8-bit bus working triple duty to transfer 8 data bits, 14 address bits, and two status bits. The small package requires about 30 TTL support chips to interface to memory. For example, the 14-bit address, which can access "16 K × 8 bits of memory", needs to be latched by some of this logic into an external memory address register (MAR). The 8008 can access 8 input ports and 24 output ports.
For controller and CRT terminal use, this is an acceptable design, but it is rather cumbersome to use for most other tasks, at least compared to the next generations of microprocessors. A few early computer designs were based on it, but most would use the later and greatly improved Intel 8080 instead.
The subsequent 40-pin NMOS Intel 8080 expanded upon the 8008 registers and instruction set and implements a more efficient external bus interface (using the 22 additional pins). Despite a close architectural relationship, the 8080 was not made binary compatible with the 8008, so an 8008 program would not run on an 8080. However, as two different assembly syntaxes were used by Intel at the time, the 8080 could be used in an 8008 assembly-language backward-compatible fashion.[irrelevant citation]
The Intel 8085 is an electrically modernized version of the 8080 that uses depletion-mode transistors and also added two new instructions.[irrelevant citation]
The Intel 8086, the original x86 processor, is a non-strict extension of the 8080, so it loosely resembles the original Datapoint 2200 design as well. Almost every Datapoint 2200 and 8008 instruction has an equivalent not only in the instruction set of the 8080, 8085, and Z80, but also in the instruction set of modern x86 processors (although the instruction encodings are different).[irrelevant citation]
The 8008 architecture includes the following features:
The following 8008 assembly source code is for a subroutine named
MEMCPY that copies a block of data bytes of a given size from one location to another.
001700 000 001701 000 001702 000 001703 000 001704 000 001705 000 002000 066 304 002002 056 003 002004 327 002005 060 002006 317 002007 302 002010 261 002011 053 002012 302 002013 024 001 002015 320 002016 301 002017 034 000 002021 310 002022 066 300 002024 056 003 002026 302 002027 207 002030 340 002031 060 002032 301 002033 217 002034 350 002035 364 002036 337 002037 066 302 002041 056 003 002043 302 002044 207 002045 340 002046 060 002047 301 002050 217 002051 350 002052 364 002053 373 002054 104 007 004 002057
; MEMCPY -- ; Copy a block of memory from one location to another. ; ; Entry parameters ; SRC: 14-bit address of source data block ; DST: 14-bit address of target data block ; CNT: 14-bit count of bytes to copy ORG 1700Q ;Data at 001700q SRC DFB 0 ;SRC, low byte DFB 0 ; high byte DST DFB 0 ;DST, low byte DFB 0 ; high byte CNT DFB 0 ;CNT, low byte DFB 0 ; high byte ORG 2000Q ;Code at 002000q MEMCPY LLI CNT+0 ;HL = addr(CNT) LHI CNT+1 LCM ;BC = CNT INL LBM LOOP LAC ;If BC = 0, ORB RTZ ;Return DECCNT LAC ;BC = BC - 1 SUI 1 LCA LAB SBI 0 LBA GETSRC LLI SRC+0 ;HL = addr(SRC) LHI SRC+1 LAC ;HL = SRC + BC ADM ;E = C + (HL) LEA ;(lower sum) INL ;point to upper SRC LAB ACM ;H = B + (HL) + CY LHA ;(upper sum) LLE ;L = E LDM ;Load D from (HL) GETDST LLI DST+0 ;HL = addr(DST) LHI DST+1 LAC ;HL = DST + BC ADM ;ADD code same as above LEA INL LAB ACM LHA LLE LMD ;Store D to (HL) JMP LOOP ;Repeat the loop END
In the code above, all values are given in octal. Locations
CNT are 16-bit parameters for the subroutine named
MEMCPY. In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored in little-endian format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with the
CNT parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode.