LatticeMico32
DesignerLattice Semiconductor
Bits32-bit
Introduced2006; 16 years ago (2006)
DesignRISC
TypeRegister-Register
EncodingFixed 32-bit
BranchingCompare and branch
EndiannessBig
ExtensionsUser-defined
OpenYes, royalty free
Registers
General purpose32

LatticeMico32 is a 32-bit microprocessor reduced instruction set computer (RISC) soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.

LatticeMico32 is licensed under a free (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture (FPGA, application-specific integrated circuit (ASIC), or software emulation, e.g., QEMU). It is possible to embed a LatticeMico32 core into Xilinx and Altera FPGAs, in addition to the Lattice Semiconductor parts the LatticeMico32 was developed for. AMD PowerTune uses LatticeMico32.[1]

The CPU core and the development toolchain are available as source-code, allowing third parties to implement changes to the processor architecture.

Features

Toolchain

See also

References

  1. ^ "AMD x86 SMU firmware analysis". 2014-12-27.