In computer architecture and engineering, a sequencer or microsequencer generates the addresses used to step through the microprogram of a control store. It is used as a part of the control unit of a CPU or as a stand-alone generator for address ranges.
Usually the addresses are generated by some combination of a counter, a field from a microinstruction, and some subset of the instruction register. A counter is used for the typical case, that the next microinstruction is the one to execute. A field from the microinstruction is used for jumps, or other logic.
Since CPUs implement an instruction set, it's very useful to be able to decode the instruction's bits directly into the sequencer, to select a set of microinstructions to perform a CPU's instructions.
Most modern CISC processors use a combination of pipelined logic to process lower complexity opcodes which can be completed in one clock cycle, and microcode to implement ones that take multiple clock cycles to complete.
One of the first integrated microcoded processors was the IBM PALM Processor, which emulated all of the processor's instruction in microcode and was used on the IBM 5100, one of the first personal computers.
Recent examples of similar open-sourced microsequencer-based processors are the MicroCore Labs MCL86, MCL51 , and MCL65 cores which emulate the Intel 8086/8088, 8051 and MOS 6502 instruction sets entirely in microcode.
The Digital Scientific Corp. Meta 4 Series 16 computer system was a user-microprogrammable system first available in 1970. Branches in the microcode sequence occur in one of three ways.[1]
One more sequencing option allowed on a branch instruction is the execute (XQ) option. When specified, the single instruction at the branch address is executed, but then execution continues after the original branch instruction. The IX option can be used with the XQ option.
The IBM System/360 was a series of compatible computers introduced in 1964, many of which were microprogrammed.[2] The System/360 Model 40 is a good example of a microprogrammed machine with complex microsequencing.[3]
The microstore consists of 4,096 56-bit microinstructions that operate in a horizontal microprogramming style. The store is addressed by the 12-bit read-only address register (ROAR). Unlike most registers in the S/360 architecture, bits in the ROAR are numbered from bit 0 on the right to bit 11 on the left.
+------------+ | ROAR | +------------+ 11 0
The model 40 performs no sequential execution of microinstructions and therefore the microsequencer doesn't really branch in the conventional sense. Instead, each microinstruction specifies the address of the next one to be executed. Four fields in the microinstruction contribute to the new address.
There are essentially three combinations or formats of these fields.
When the CB field contains 15, a functional branch occurs. The bits of the new microstore address in the ROAR are determined as follows.
The CC field can specify various tests of the state of the machine. It can also specify a constant 0 or 1 for an unconditional bit.
This format alters the flow of control to 1 of 16 instruction pairs within the low 32 words of a 64-word block of microstore (because bit 5 is always 0). The CC field then determines which instruction of the pair receives control.
When the CD field is 0, 1, or 3, flow of control is directed to an instruction within the current 64-word block. The bits of the new microstore address are determined as follows.
The CA field selects 1 of 16 4-word groups within the current 64-word block. The CB and CC fields then determine which instruction of the 4 receives control.
When the CD field is 2, flow of control is directed in a nonobvious manner. The bits of the new microstore address are determined as follows:
The next instruction is in the same 1K-word region as the current instruction, because bits 11–10 remain the same. The CA field determines the 64-word block within the region. The instruction is in the same 4-word group within the new block as the current instruction is within the current block, because bits 5–2 remain the same. The CB and CC fields then determine which instruction of the 4 receives control.
This description has been simplified. It ignores the following features.