Generic 4-stage pipeline; the colored boxes represent instructions independent of each other
Generic 4-stage pipeline; the colored boxes represent instructions independent of each other

Minimal instruction set computer (MISC) is a central processing unit (CPU) architecture, usually in the form of a microprocessor, with a very small number of basic operations and corresponding opcodes, together forming an instruction set. Such sets are commonly stack-based rather than register-based to reduce the size of operand specifiers.

Such a stack machine architecture is inherently simpler since all instructions operate on the top-most stack entries.

One result of the stack architecture is an overall smaller instruction set, allowing a smaller and faster instruction decode unit with overall faster operation of individual instructions.

Characteristics and design philosophy

Separate from the stack definition of a MISC architecture, is the MISC architecture being defined by the number of instructions supported.

Also, the instruction pipelines of MISC as a rule tend to be very simple. Instruction pipelines, branch prediction, out-of-order execution, register renaming, and speculative execution broadly exclude a CPU from being classified as a MISC architecture.

While 1-bit CPUs are otherwise obsolete (and were not MISCs nor OISCs), the first carbon nanotube computer is a 1-bit one-instruction set computer, and has only 178 transistors, and thus likely the lowest-complexity (or next-lowest) CPU produced so far (by transistor count).


Some of the first digital computers implemented with instruction sets were by modern definition minimal instruction set computers.

Among these various computers, only ILLIAC and ORDVAC had compatible instruction sets.

Early stored-program computers

Design weaknesses

The disadvantage of a MISC is that instructions tend to have more sequential dependencies, reducing overall instruction-level parallelism.

MISC architectures have much in common with some features of some programming languages such as Forth's use of the stack, and the Java virtual machine. Both are weak in providing full instruction-level parallelism.

Notable CPUs

Probably the most commercially successful MISC was the original INMOS transputer architecture that had no floating-point unit. However, many 8-bit microcontrollers, for embedded computer applications, qualify as MISC.

Each STEREO spacecraft includes two P24 MISC CPUs and two CPU24 MISC CPUs.[9][10]

See also


  1. ^ Ting, Chen-hanson; Moore, Charles H. (1995). "MuP21: A High Performance MISC Processor". UltraTechnology. Offete Enterprises, Inc.
  2. ^ US patent 5481743A, Baxter, Michael A., "Minimal instruction set computer architecture and multiple instruction issue method", published 1996-01-02, issued 1996-01-02, assigned to Apple Inc. 
  3. ^ Baxter, Michael A. (1993). "Minimal instruction set computer architecture and multiple instruction issue method". Google.
  4. ^ Halverson, Richard, Jr.; Lew, Art (1995). "An FPGA-Based Minimal Instruction Set Computer". CiteSeerX. The Pennsylvania State University. p. 23.
  5. ^ Kong, J.H.; Ang, L.-M.; Seng, K.P. "Minimal Instruction Set AES Processor using Harvard Architecture". 2010. doi:10.1109/ICCSIT.2010.5564522
  6. ^ Robertson, James E. (1955). Illiac Design Techniques: report number UIUCDCS-R-1955-146 (Report). Urbana–Champaign, Illinois: Digital Computer Laboratory, University of Illinois at Urbana–Champaign.
  7. ^ US patent 2636672, Hamilton, Francis E.; Hughes, Ernest S. Jr. & Rowley, Russell A. et al., "Selective Sequence Electronic Calculator", issued 1953-04-28, assigned to IBM 
  8. ^ Grosch, Herbert R.J. (1991). Computer: Bit Slices From a Life. Third Millenium Books. ISBN 978-0-8873-3085-8.
  9. ^ Mewaldt, R. A.; Cohen, C. M. S.; Cook, W. R.; Cummings, A. C.; et al. The Low-Energy Telescope (LET) and SEP Central Electronics for the STEREO Mission (PDF) (Report).
  10. ^ Russell, C.T. (2008). The STEREO Mission (Report).