Process variation is the naturally occurring variation in the attributes of transistors (length, widths, oxide thickness) when integrated circuits are fabricated. The amount of process variation becomes particularly pronounced at smaller process nodes (<65 nm) as the variation becomes a larger percentage of the full length or width of the device and as feature sizes approach the fundamental dimensions such as the size of atoms and the wavelength of usable light for patterning lithography masks.
Process variation causes measurable and predictable variance in the output performance of all circuits but particularly analog circuits due to mismatch.[1] If the variance causes the measured or simulated performance of a particular output metric (bandwidth, gain, rise time, etc.) to fall below or rise above the specification for the particular circuit or device, it reduces the overall yield for that set of devices.
The first mention of variation in semiconductors was by William Shockley, the co-inventor of the transistor, in his 1961 analysis of junction breakdown.[2]
An analysis of systematic variation was performed by Schemmert and Zimmer in 1974 with their paper on threshold-voltage sensitivity.[3] This research looked into the effect that the oxide thickness and implantation energy had on the threshold voltage of MOS devices.
sources of variations 1) gate oxide thickness 2) random dopant fluctuations 3) Device Geometry, Lithography in nanometer region
Semiconductor foundries run analyses on the variability of attributes of transistors (length, width, oxide thickness, etc.) for each new process node. These measurements are recorded and provided to customers such as fabless semiconductor companies. This set of files are generally referred to as "model files" in the industry and are used by EDA tools for simulation of designs.
Typically process models (example HSPICE ) include process corners based on Front End Of Line conditions. These often are centered at a typical or nominal point and will also contain Fast and Slow corners often separated into Ntype and Ptype corners that affect the non-linear active N+ / P+ devices in different ways. Examples are TT for nominal N+ and P+ transistors, FF for fast N+ and P+ transistors, FS for fast N+ and slow P+ transistors, etc.
|
See also: Back end of line |
When modeling the parasitic wiring an orthogonal set of process corners is often supplied with the parasitic extraction deck. (Example STAR-RC extraction deck). These corners are usually listed as Typical/Nominal for the target value and Cbest / Cworst corners for the variations in: conductor thickness, conductor width, and conductor oxide thickness that result in the Least / Most capacitance on the wiring. Often an additional corner called RCbest and RCworst is supplied that picks the conductor parameters that result in the Best (lowest) and worst (highest) wiring resistance for thickness and width, and then adds the oxide thickness that adds the Best (lowest) and Worst (highest) capacitance due to the oxide thickness as this value is not directly correlated to wiring resistance.
Designers using this approach run from tens to thousands of simulations to analyze how the outputs of the circuit will behave according to the measured variability of the transistors for that particular process. The measured criteria for transistors are recorded in model files given to designers for simulating their circuits before simulation.
The most basic approach used by designers is increasing the size of devices which are sensitive to mismatch.
This is used to reduce variation due to polishing, etc.[4]
To reduce roughness of line edges, advanced lithography techniques are used.