DesignerMIPS Computer Systems

The R3000 is a 32-bit RISC microprocessor chipset developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in June 1988, it was the second MIPS implementation, succeeding the R2000 as the flagship MIPS microprocessor. It operated at 20, 25 and 33.33 MHz.

The MIPS 1 instruction set is small compared to those of the contemporary 80x86 and 680x0 architectures, encoding only more commonly used operations and supporting few addressing modes. Combined with its fixed instruction length and only three different types of instruction formats, this simplified instruction decoding and processing. It employed a 5-stage instruction pipeline, enabling execution at a rate approaching one instruction per cycle, unusual for its time.

This MIPS generation supports up to four co-processors. In addition to the CPU core, the R3000 microprocessor includes a Control Processor (CP), which contains a Translation Lookaside Buffer and a Memory Management Unit.[1] The CP works as a coprocessor. Besides the CP, the R3000 can also support an external R3010 numeric coprocessor and two other external coprocessors.

The R3000 CPU does not include level 1 cache. Instead, its on-chip cache controller operates external data and instruction caches of up to 256 KB each. It can access both caches during the same clock cycle.

The R3000 found much success and was used by many companies in their workstations and servers. Users included:

The R3000 was also used as an embedded microprocessor. When advances in technology rendered it obsolete for high-performance systems, it found continued use in lower-cost designs. Companies such as LSI Logic developed derivatives of the R3000 specifically for embedded systems.

The R3000 was a further development of the R2000 with minor improvements including larger TLB and a faster bus to the external caches. The R3000 die contained 115,000 transistors and measured about 75,000 square mils (48 mm2).[5] MIPS was a fabless semiconductor company, so the R3000 was fabricated by MIPS partners including Integrated Device Technology (IDT), LSI Logic, NEC Corporation, Performance Semiconductor, and others. It was fabricated in a 1.2 μm complementary metal–oxide–semiconductor (CMOS) process[1] with two levels of aluminium interconnect.

MIPS R3000A die shot
MIPS R3000A die shot

Derivatives of the R3000 for non-embedded applications include:

Derivatives of the R3000 for embedded applications include:


  1. ^ a b Jurij Šilc; Borut Robič; Theo Ungerer (1999). Processor Architecture: From Dataflow to Superscalar and Beyond. Springer-Verlag Berlin Heidelberg. p. 38. ISBN 978-3-540-64798-0.
  2. ^ Sharma, Aashish (21 July 2015). "The Original PlayStation CPU is Powering New Horizons". Fossbytes.
  3. ^ Tomson, Iain (14 January 2015). "PlayStation-processor-powered plutonium probe prepares Pluto pics". The Register.
  4. ^ Dockrill, Peter (17 July 2015). "NASA's New Horizon Probe Made It to Pluto With a PlayStation CPU For a Brain". Science Alert.
  5. ^ Michael Slater, ed. (1992). A Guide to RISC microprocessors. Academic Press, Inc. p. 129. ISBN 978-0-12-649140-1.

Further reading