Overall single socket and multi-socket throughput increased with the T3 processor in systems, providing superior throughput with half the CPU socket requirements to its predecessor.
The throughput (SPEC CINT2006 rate) increased in single a socket T3-1 platform[6] in comparison to its predecessor T2+ processor in a dual-socket T5240 platform.[7]
Under simulated web serving workloads, dual-socket based SPARC T3 systems benchmarked better performance than quad-socket (previous generation) UltraSPARC T2+ systems (as well as competing dual and quad socket contemporary systems).[8]
History
SPARC T3 processor
Online IT publication The Register incorrectly reported in June 2008 that the microprocessor would have 16 cores, each with 16 threads. In September 2009 they published a roadmap that instead showed 8 threads per core.[9] During the Hot Chips 21 conference Sun revealed the chip has a total of 16 cores and 128 threads.[10][11] According to the ISSCC 2010 presentation:
"A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to
maximize throughput. The 6MB L2 cache of 461GB/s and the 308-pin SerDes I/O of 2.4Tb/s
support the required bandwidth. Six clock and four voltage domains, as well as power
management and circuit techniques, optimize performance, power, variability and yield trade-offs
across the 377mm2 die."[12]
Support for the UltraSPARC T3 was confirmed on July 16, 2010 when the ARCBot under Twitter noted unpublished PSARC/2010/274 which revealed a new "-xtarget value for UltraSPARC T3" being included in OpenSolaris.[13]
During Oracle OpenWorld in San Francisco on September 20, 2010, the processor was officially launched as the "SPARC T3" (dropping the "Ultra" prefix in its name), accompanied by new systems and new reported benchmarks claiming world-record performance.[4] Varied real-world application benchmarks were released with full system disclosures.[14][15][16] Internationally recognized SPEC benchmarks were also released with full system disclosures.[17][18]
Oracle disclosed that SPARC T3 was built with a 40 nm process.[19]
Security co-processor on each core. Supports DES, 3DES, AES, RC4, SHA-1, SHA-256/384/512, Kasumi, Galois Field, MD5, RSA with up to 2048 key, ECC, CRC.
With the release of the SPARC T3 chip, the new brand of Oracle SPARC T-series servers was introduced to the market, effectively replacing CMT (UltraSPARC T2/T2 Plus) machines from the previous SPARC Enterprise product line. Fewer physical products from the former server line were refreshed with the T3 chip, reducing the total number of servers respectively to four:[20]
Like the prior T1, T2, and T2+ processors, the T3 supports Hyper-Privileged execution mode. The T3 supports up to 128 Oracle VM Server for SPARC domains (a feature formerly known as Logical Domains).[24]
Performance improvement versus T2 and T2+
The SPARC T3 processor is effectively two T2+ processors on a single die.[25] The T3 has:
Double the cores (16) of a T2 or T2+
Double the 10Gig Ethernet ports (2) over a T2+
Double the crypto accelerator cores (16) over a T2 or T2+
^J. Shin, K. Tam, D. Huang, B. Petrick, H. Pham, C. Hwang, H. Li, A. Smith, T. Johnson,
F. Schumacher, D. Greenhill, A. Leon, A. Strong. "A 40nm 16-Core 128-Thread CMT SPARC SoC Processor". ISSCC 2010.
