| General information | |
|---|---|
| Launched | 1976 |
| Designed by | Scientific Micro Systems (SMS) |
| Common manufacturer(s) |
|
| Performance | |
| Max. CPU clock rate | to 8 MHz |
| Data width | 16 instruction, 8 data |
| Address width | 13 instruction, 1 data |
| Architecture and classification | |
| Number of instructions | 8 |
| Physical specifications | |
| Package(s) |
|
| History | |
| Successor(s) | 8X305 |
The 8X300 is a microprocessor produced and marketed by Signetics starting 1976 as a second source for the SMS 300 by Scientific Micro Systems, Inc.[1][2][3][4] Although SMS developed the SMS 300, Signetics was the sole manufacturer of this product line. In 1978 Signetics purchased the rights to the SMS 300 series and renamed it 8X300.
It was designed to be a fast microcontroller and signal processor, and because of this differs considerably from conventional NMOS logic microprocessors of the time. Perhaps the major difference was that it was implemented with bipolar Schottky transistor technology, and could fetch, decode and execute an instruction in only 250 ns. Data could be input from one device, modified, and output to another device during one instruction cycle.
In 1982, Signetics released an improved and faster version, the 8X305. This processor went on to become very popular in military applications and was second-sourced by Advanced Micro Devices as the AM29X305. Eventually, production rights were sold to Lansdale Semiconductor Inc., who was still offering the 8X305 as of 2017.[5] A clone of the 8X300 was manufactured in the Soviet Union under the designation KM1818VM01 (Russian: КМ1818ВМ01).[4]
The device was supplied in a 50-pin DIL ceramic package and runs from a single 5V supply rail. An external pass transistor is required to complete an on-chip voltage regulator, which supplies 3V to selected areas of the chip. This helps contain the total current drain to less than 450mA.
Clock requirements are met by connecting an 8 MHz crystal directly to two pins. Alternatively, out of phase signals from an external clock generator can be used.
A second unique feature is a dedicated 13-bit address and 16-bit data bus to access program memory, allowing 8192 16-bit program words to be directly addressed. This allows ROM / PROM program memories to be directly connected without further hardware. A second combined 8-bit address/data bus, the Interface Vector (IV) bus, is used for data and I/O. Two control signals, WC (write command) and SC (select command), determine the state of the IV bus as follows:
A further two signals, LB (left bank select) and RB (right bank select), effectively double the IV bus address space and were most often used to switch between RAM memory in one bank and I/O ports in the other.
Another unusual feature is that rather than execute mask, rotate, shift and merge instructions in the arithmetic logic unit (ALU), as is the case with most microprocessors, the 8X300 has separate mask, rotate, shift and merge units. Data can therefore be rotated, masked, modified, shifted and merged (in that order), all in one instruction cycle.
The processor normally manipulates 8-bit data bytes, but the mask unit makes it possible to manipulate single or multiple bits, making this a variable data-length processor. Internal data is stored in 8-bit read/write registers—R1 through R6, R9, and an auxiliary register (R0). The auxiliary register holds one of the operands used in two-operand instructions, such as ADD or AND, and a single-bit (read only) overflow register (R8) stores the carry-over bit from ADD operations. Two virtual write only registers IVL (R7) and IVR (R15) are used to put an address on the IV bus, and two sets of eight virtual registers (R16-R23 and R24-R31) are used to transfer data to or from the IV bus. In the latter case, the upper two bits of the register number select the left or right bank, and the lower three bits define the number of places the data is to be rotated. An 8-bit IV-bus buffer retains a copy of the last data to be transferred to or from the IV bus. This data is used in Merge operations.
The three most significant bits of the instruction define the opcode, and divide the instructions into eight classes:
The use of the remaining 13 bits of the instruction depends on the opcode:
The rotate and mask units are located between the register bank and the ALU. Therefore, all data can, in principle, be rotated and masked before it enters the ALU.
The Shift and Merge units are located between the ALU and the IV bus, and any data sent to IV bus can therefore be shifted and merged before being output.
Note: a count of zero for the number of bits to merge will result in all 8 bits being replaced.
The following combinations are possible, depending on the source and destination:
Transferring data to and from the 8X300 is a two-step process:
Because the I/O address is output separately, the I/O ports must hold (latch) the selection. This can be done with separate address decoders and latches, or with an I/O port with integrated address decoding and latching, such as the 8X32. Because of the latching, I/O ports, once addressed, remain active until a different address is output, and can be accessed multiple times without the need to address them again. Two I/O ports (or RAM addresses) can be active at the same time, using the Bank Select signals to rapidly switch between them without further addressing.
In an extensive application note, Signetics showed how to use the 8X300 as a floppy disk controller. A revised application note showed the use of the 8X300 together with the 8X330. Other application notes described:
A demonstration system (contained in a briefcase) and application note showed the 8X300 being used in a traffic-light controller.
Olivetti used the 8X300 and later 8X305 as the controller for the ST506 hard disk in the M20 personal computer series.
Convergent Technologies used the 8X300, 8X320, and 8X330 in their AWS hard disk controller in 1981.[6]
Western Digital used the 8X300 in their WD1000 ST506 hard disk controller and the 8X305 in their WD1001 ECC hard disk controller.[7]
