A simple model of spin-transfer torque for two anti-aligned layers. Current flowing out of the fixed layer is spin-polarized. When it reaches the free layer the majority spins relax into lower-energy states of opposite spin, applying a torque to the free layer in the process.
A schematic diagram of a spin valve/magnetic tunnel junction. In a spin valve the spacer layer (purple) is metallic; in a magnetic tunnel junction it is insulating.

Spin-transfer torque (STT) is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction or spin valve can be modified using a spin-polarized current.

Charge carriers (such as electrons) have a property known as spin which is a small quantity of angular momentum intrinsic to the carrier. An electric current is generally unpolarized (consisting of 50% spin-up and 50% spin-down electrons); a spin polarized current is one with more electrons of either spin. By passing a current through a thick magnetic layer (usually called the “fixed layer”), one can produce a spin-polarized current. If this spin-polarized current is directed into a second, thinner magnetic layer (the “free layer”), the angular momentum can be transferred to this layer, changing its orientation. This can be used to excite oscillations or even flip the orientation of the magnet. The effects are usually seen only in nanometer scale devices.

Spin-transfer torque memory

Spin-transfer torque can be used to flip the active elements in magnetic random-access memory. Spin-transfer torque magnetic random-access memory (STT-RAM or STT-MRAM) is a non-volatile memory with near-zero leakage power consumption which is a major advantage over charge-based memories such as SRAM and DRAM. STT-RAM also has the advantages of lower power consumption and better scalability than conventional magnetoresistive random-access memory (MRAM) which uses magnetic fields to flip the active elements.[1] Spin-transfer torque technology has the potential to make possible MRAM devices combining low current requirements and reduced cost; however, the amount of current needed to reorient the magnetization is presently too high for most commercial applications, and the reduction of this current density alone is the basis for present academic research in spin electronics.[2]

Industrial development

Sony Research Center published the first Japan Patent application for S.P.I.N.O.R. (Spin Polarized Injection Non-Volatile Orthogonal Read/Write RAM), a forerunner of STT RAM, in 1997.[3] Subsequently, at IEDM 2005, Sony researchers reported the first working 4kb STT memory, dubbed Spin-RAM, with replacement of the paramagnetic spacer layer of SPINOR memory with MgO dielectric.[4]

Hynix Semiconductor and Grandis formed a partnership in April 2008 to explore commercial development of STT-RAM technology.[5][6]

Hitachi and Tohoku University demonstrated a 32-Mbit STT-RAM in June 2009.[7]

On August 1, 2011, Grandis announced that it had been purchased by Samsung Electronics for an undisclosed sum.[8]

In 2011, Qualcomm presented a 1 Mbit Embedded STT-MRAM, manufactured in TSMC's 45 nm LP technology at the Symposium on VLSI Circuits.[9]

In May 2011, Russian Nanotechnology Corp. announced an investment of $300 million in Crocus Nano Electronics (a joint venture with Crocus Technology) which will build an MRAM factory in Moscow, Russia.

In 2012 Everspin Technologies released the first commercially available DDR3 dual in-line memory module ST-MRAM which has a capacity of 64 Mb.[10]

In June 2019 Everspin Technologies started pilot production for 28 nm 1 Gb STT-MRAM chips.[11]

In December 2019 Intel demonstrated STT-MRAM for L4-cache [12]

In 2022 TechInsights finds 16Mb embedded STT-MRAM memory in the FitBit Luxe fitness tracker's MCU and that of several other commercially available wearable products. [13]

Other companies working on STT-RAM include Avalanche Technology, Crocus Technology[14] and Spin Transfer Technologies.[15]

See also

References

  1. ^ Bhatti, Sabpreet; Sbiaa, Rachid; Hirohata, Atsufumi; Ohno, Hideo; Fukami, Shunsuke; Piramanayagam, S.N (2017). "Spintronics based random access memory: A review". Materials Today. 20 (9): 530. doi:10.1016/j.mattod.2017.07.007. hdl:10356/146755.
  2. ^ Ralph, D. C.; Stiles, M. D. (April 2008). "Spin transfer torques". Journal of Magnetism and Magnetic Materials. 320 (7): 1190–1216. arXiv:0711.4608. Bibcode:2008JMMM..320.1190R. doi:10.1016/j.jmmm.2007.12.019. ISSN 0304-8853. S2CID 3209246.
  3. ^ Maiken, Eric. "Nonvolatile random access memory device". patents.google.com. Japan Patent Office. Retrieved 20 May 2023.
  4. ^ Hosomi, M (December 2005). "A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-ram". IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest. pp. 459–462. doi:10.1109/IEDM.2005.1609379. ISBN 0-7803-9268-X. S2CID 17635524. Retrieved 20 May 2023. ((cite book)): |journal= ignored (help)
  5. ^ "Grandis press release describing partnership with Hynix" (PDF). Grandis. 1 April 2008. Archived from the original (PDF) on 14 April 2012. Retrieved 2008-08-15.
  6. ^ "Hynix press release describing partnership with Grandis". Hynix. 2 April 2008. Retrieved 15 August 2008.[dead link]
  7. ^ "Session 8-4: 32-Mb 2T1R SPRAM with localized bi-directional write driver and '1'/'0' dual-array equalized reference cell". vlsisymposium.org. Archived from the original on 12 March 2012.
  8. ^ [1][permanent dead link]
  9. ^ Kim, J.P.; Qualcomm Inc., San Diego, CA, USA; Taehyun Kim; Wuyang Hao; Rao, H.M.; Kangho Lee; Xiaochun Zhu; Xia Li; Wah Hsu; Kang, S.H.; Matt, N.; Yu, N. (15–17 June 2011). A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance. 2011 Symposium on VLSI circuits (VLSIC). ieeexplore.ieee.org. IEEE. ISBN 978-1-61284-175-5. ISSN 2158-5601. Archived from the original on 1 July 2017. Retrieved 30 November 2019.((cite conference)): CS1 maint: multiple names: authors list (link)
  10. ^ "Everspin ships first ST-MRAM memory with 500X performance of flash". Computerworld. 12 November 2012. Retrieved 25 September 2014.
  11. ^ "Everspin enters pilot production phase for the world's First 28 nm 1 Gb STT-MRAM component | Everspin". www.everspin.com. Retrieved 25 June 2019.
  12. ^ "Intel demonstrates STT-MRAM for L4 cache". 10 December 2019.
  13. ^ "TSMC 22ULL eMRAM Die removed from Ambiq™ Apollo4 cache". 20 June 2023.
  14. ^ "Crocus press release describing MRAM new prototype". crocus-technology.com. Crocus. 1 October 2009. Archived from the original on 20 April 2012.
  15. ^ "Interview with Vincent Chun from Spin transfer technologies". Mram-info.com. Retrieved 7 February 2014.

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