XDR2 DRAM was a proposed type of dynamic random-access memory that was offered by Rambus. It was announced on July 7, 2005[1] and the specification for which was released on March 26, 2008.[citation needed] Rambus has designed XDR2 as an evolution of, and the successor to, XDR DRAM.
XDR2 DRAM is intended for use in high-end graphics cards and networking equipment.
As a fabless semiconductor company, Rambus only produces a design; it must make deals with memory manufacturers to produce XDR2 DRAM chips, and there has been a notable lack of interest in doing so.[2]
In addition to a higher clock rate (up to 800 MHz), the XDR2 differential data lines transfer data at 16 times the system clock rate, transferring 16 bits per pin per clock cycle. This "Hexadecimal Data Rate" is twice XDR's 8× multiplier. The basic burst size has also doubled.
Unlike XDR, memory commands are also transmitted over differential point-to-point links at this high data rate. The command bus varies between 1 and 4 bits wide. Even though each bit requires 2 wires, this is still less than the 12-wire XDR request bus, but it must grow with the number of chips addressed.
There is a basic limit to how frequently data can be fetched from the currently open row. This is typically 200 MHz for standard SDRAM and 400–600 MHz for high-performance graphics memory. Increasing interface speeds require fetching larger blocks of data in order to keep the interface busy without violating the internal DRAM frequency limit. At 16×800 MHz, to stay within a 400 MHz column access rate would require a 32-bit burst transfer. Multiplied by a 32-bit wide chip, this is a minimum fetch of 128 bytes, inconveniently large for many applications.
Typical memory chips are internally divided into 4 quadrants, with left and right halves connected to different halves of the data bus, and top or bottom halves being selected by bank number. (Thus, in a typical 8-bank DRAM, there would be 4 half-banks per quadrant.) XDR2 permits independently addressing each quadrant, so the two halves of the data bus can fetch data from different banks. Additionally, the data fetched from each half-bank is only half of what is needed to keep the data bus full; accesses to an upper half-bank must be alternated with access to a lower half-bank.
This effectively doubles the number of banks and reduces the minimum data access size by a factor of 4, albeit with the limitation that accesses must be spread uniformly across all 4 quadrants.[3][4]