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((Use dmy dates|date=January 2024))
((more citations needed|date=June 2023))

'''Altera Hardware Description Language''' ('''AHDL''') is a proprietary [[hardware description language]] (HDL) developed by [[Altera Corporation]]. AHDL is used for [[digital logic]] design entry for Altera's [[complex programmable logic device]]s (CPLDs) and [[field-programmable gate array]]s (FPGAs). It is supported by Altera's MAX-PLUS and [[Altera Quartus|Quartus]] series of design software.<ref>((cite book |title=MAX+PLUS II AHDL |date=November 1995 |publisher=Altera Corporation |location=San Jose, CA|edition=6.0 |url=https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset01/altera-ahdl-language-reference.pdf |access-date=23 June 2023))</ref> AHDL has an [[Ada programming language|Ada]]-like syntax and its feature set is comparable to the synthesizable portions of the [[Verilog]] and [[VHDL]] hardware description languages. In contrast to HDLs such as Verilog and VHDL, AHDL is a design-entry language only; all of its language constructs are synthesizable. By default, Altera software expects AHDL source files to have a .tdf extension (Text Design Files).

==Example==
<pre>
% a simple AHDL up counter, released to public domain 13 November 2006 %
% [block quotations achieved with percent sign] %
% like c, ahdl functions must be prototyped %

% PROTOTYPE:
 FUNCTION COUNTER (CLK)
	RETURNS (CNTOUT[7..0]); %

% function declaration, where inputs, outputs, and
bidirectional pins are declared %
% also like c, square brackets indicate an array %

SUBDESIGN COUNTER
(
	CLK		:INPUT;
	CNTOUT[7..0]	:OUTPUT;
)

% variables can be anything from flip-flops (as in this case),
tri-state buffers, state machines, to user defined functions %

VARIABLE
	TIMER[7..0]: DFF;

% as with all hardware description languages, think of this
 less as an algorithm and more as wiring nodes together %

BEGIN
	DEFAULTS

		TIMER[].prn = VCC; %  this takes care of d-ff resets %
		TIMER[].clrn = VCC;
	END DEFAULTS;

	TIMER[].d = TIMER[].q + H"1";
END;

</pre>

==References==
((reflist))
* Scarpino, Frank A., ''VHDL and AHDL Digital System Implementation''. Prentice Hall PTR, 1998.

((Programmable Logic))

[[Category:Hardware description languages]]


((electronics-stub))

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