|Type of RAM|
|Type||Synchronous dynamic random-access memory|
|Release date||July 14, 2020|
|Clock rate||2,000–4,000 MHz|
|Transfer rate||4,000–8,000 MT/s|
|Voltage||1.1 V nominal (actual levels are regulated by on-the-module regulators)|
|Predecessor||DDR4 SDRAM (2014)|
Double Data Rate 5 Synchronous Dynamic Random-Access Memory (DDR5 SDRAM) is a type of synchronous dynamic random-access memory. Compared to its predecessor DDR4 SDRAM, DDR5 was planned to reduce power consumption, while doubling bandwidth. The standard, originally targeted for 2018, was released on July 14, 2020.
A new feature called Decision Feedback Equalization (DFE) enables I/O speed scalability for higher bandwidth and performance improvement. DDR5 supports more bandwidth than its predecessor, DDR4, with 4.8 gigabits per second possible, but not shipping at launch. DDR5 has about the same latency as DDR4 and DDR3. DDR5 octuples the maximum DIMM capacity from 64 GB to 512 GB. DDR5 also has higher frequencies than DDR4.
Rambus announced a working DDR5 DIMM in September 2017. On November 15, 2018, SK Hynix announced completion of its first DDR5 RAM chip; running at 5200 MT/s at 1.1 V. In February 2019, SK Hynix announced a 6400 MT/s chip, the highest speed specified by the preliminary DDR5 standard. Some companies were planning to bring the first products to market by the end of 2019. The world's first DDR5 DRAM chip was officially launched by SK Hynix on October 6, 2020.
The separate JEDEC standard LPDDR5 (Low Power Double Data Rate 5), intended for laptops and smartphones, was released in February 2019.
Compared to DDR4, DDR5 further reduces memory voltage to 1.1 V, thus reducing power consumption. DDR5 modules incorporate on-board voltage regulators in order to reach higher speeds. DDR5 supports a speed of 51.2 GB/s per module and two memory channels per module.
There is a general expectation that most use-cases that currently use DDR4 will eventually migrate to DDR5.
In August 2021, Samsung revealed a 512 GB 7200 MT/s RAM DIMM.
Unlike DDR4, all DDR5 chips have on-die ECC, where errors are detected and corrected before sending data to the CPU. This, however, is not the same as true ECC memory with extra data correction chips on the memory module. DDR5's on-die error correction is to improve reliability and to allow denser RAM chips which lowers the per-chip defect rate. There still exist non-ECC and ECC DDR5 DIMM variants; the ECC variants have extra data lines to the CPU to send error-detection data, letting the CPU detect and correct errors occurring in transit.
Each DDR5 DIMM has two independent channels. Earlier DIMM generations featured only a single channel and one CA (Command/Address) bus controlling the whole memory module with its 64 (for non-ECC) or 72 (for ECC) data lines. Both subchannels on a DDR5 DIMM each have their own CA bus, controlling 32 bits for non-ECC memory and either 36 or 40 data lines for ECC memory, resulting in a total number of either 64, 72 or 80 data lines. The reduced bus width is compensated by a doubled minimum burst length of 16, which preserves the minimum access size of 64 bytes, which matches the cache line size used by modern x86 microprocessors.
For use in personal computers and servers, multiple DDR5 memory chips are usually mounted on a circuit board to form memory modules, more commonly known as DIMMs. As with previous memory generations, there are multiple DIMM variants available for DDR5.
Unbuffered memory modules (UDIMMs) directly expose the memory chip interface to the module connector. Registered or load-reduced variants (RDIMMs/LRDIMMs) use additional active circuitry on the memory module in order to buffer the signals between the memory controller and the DRAM chips. This reduces the capacitive load on the DDR5 bus.
DDR5 RDIMMs/LRDIMMs use 12 V and UDIMMs use 5 V input. In order to prevent damage by accidental insertion of the wrong memory type, DDR5 UDIMMs and (L)RDIMMs are not mechanically compatible. Additionally, DDR5 DIMMs are supplied with management interface power at 3.3 V, and use on-board circuitry (a power management integrated circuit and associated passive components) to convert to the lower voltage required by the memory chips. Final voltage regulation close to the point of use provides more stable power, and mirrors the development of voltage regulator modules for CPU power supplies.
Standard DDR5 memory speeds range from 4000 to 6400 million transfers per second (PC5-32000 to PC5-51200). Higher speeds may be added later, as happened with previous generations.
Compared to DDR4 SDRAM, the minimum burst length was doubled to 16, with the option of "burst chop" after eight transfers. The addressing range is also slightly extended as follows:
|Command||CS||Command/address (CA) bits|
(Open a row)
|L||L||L||Row R0–3||Bank||Bank group||Chip CID0–2|
|Reserved for future use||L||H||L||L||L||V|
|Write pattern||L||H||L||L||H||L||H||Bank||Bank group||Chip CID0–2|
|Reserved for future use||L||H||L||L||H||H||V|
|Mode register write||L||H||L||H||L||L||Address MRA0–7||V|
|Mode register read||L||H||L||H||L||H||Address MRA0–7||V|
|Write||L||H||L||H||H||L||BL||Bank||Bank group||Chip CID0–2|
|Read||L||H||L||H||H||H||BL||Bank||Bank group||Chip CID0–2|
|Vref CA||L||H||H||L||L||L||Opcode OP0-6||L||V|
|Vref CS||L||H||H||L||L||L||Opcode OP0-6||H||V|
|Refresh all||L||H||H||L||L||H||CID3||V||H||L||Chip CID0–2|
|Refresh management all||L||H||H||L||L||H||CID3||V||L||Chip CID0–2|
|Refresh same bank||L||H||H||L||L||H||CID3||Bank||V||H||Chip CID0–2|
|Refresh management same bank||L||H||H||L||L||H||CID3||Bank||V||L||H||Chip CID0–2|
|Precharge all||L||H||H||L||H||L||CID3||V||L||Chip CID0–2|
|Precharge same bank||L||H||H||L||H||L||CID3||Bank||V||H||Chip CID0–2|
|Precharge||L||H||H||L||H||H||CID3||Bank||Bank group||Chip CID0–2|
|Reserved for future use||L||H||H||H||L||L||V|
|Multi-purpose command||L||H||H||H||H||L||Opcode OP0–7||V|
|Deselect (no operation)||H||X|
The command encoding was significantly rearranged and takes inspiration from that of LPDDR4; commands are sent using either one or two cycles with 14-bit bus. Some simple commands (e.g. precharge) take one cycle, while any that include an address (activate, read, write) use two cycles to include 28 bits of information.
Also like LPDDR, there are now 256 8-bit mode registers, rather than 8 13-bit mode registers. Also, rather than one register (MR7) being reserved for use by the registered clock driver chip, a complete second bank of mode registers is defined (selected using the CW bit).
The "Write Pattern" command is new for DDR5; this is identical to a write command, but the range is filled in with copies of a one-byte mode register (which defaults to all-zero) instead of individual data. Although this normally takes the same amount of time as a normal write, not driving the data lines saves energy. Also, writes to multiple banks may be interleaved more closely as the command bus is freed earlier.
The multi-purpose command includes various sub-commands for training and calibration of the data bus.
12th generation Alder Lake and 13th generation Raptor Lake CPUs support both DDR5 and DDR4 but, usually, there are only DIMM sockets for either one or the other on a motherboard. Some mainboards with Intel's H610 chipset support both DDR4 and DDR5, but not simultaneously.
DDR5 and LPDDR5 are supported by AMD's Ryzen 6000 series mobile APUs, powered by their Zen 3+ architecture. Ryzen 7000 series desktop processors also support DDR5 memory as standard.
Epyc 4th gen Genoa and Bergamo server CPUs have support for 12-channel DDR5 on the SP5 socket.
VIN_BULK[:] 12 V power input supply pin to the PMIC. VIN_MGMT[:] 3.3 V power input supply pin to the PMIC for VOUT_1.8V & VOUT_1.0V LDO output,side band management access, internal memory read opera- tion.