System/360
DesignerIBM
Bits32-bit
IntroducedApril 7, 1964; 58 years ago (1964-04-07)
DesignCISC
TypeRegister-Register
Register-Memory
Memory-Memory
EncodingVariable (2, 4 or 6 bytes long)
BranchingCondition code, indexing, counting
EndiannessBig
Page sizeN/A, except for 360/67
OpenYes
Registers
General purpose16× 32-bit
Floating point4× 64-bit

The IBM System/360 architecture is the model independent architecture for the entire S/360 line of mainframe computers, including but not limited to the instruction set architecture. The elements of the architecture are documented in the IBM System/360 Principles of Operation[1][2] and the IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information manuals.[3]

Features

IBM S/360 registers
General Registers 0-15

Two's complement value
0 31
Floating Point Registers 0-6

S Biased exponent Mantissa
0 1 7 8 31

Mantissa (continued)
32 63
S/360 PSW[4]

Chan.
Mask
I
O
E
X
Key A M W P Interruption Code
0 1 2 4 5 6 7 8 11 12 13 14 15 16 31

ILC CC Program
Mask
Instruction Address
32 33 34 35 36 39 40 63
S/360 PSW abbreviations
Bits Field Meaning
0-5 Channel Masks for channels 0-5
6 IO I/O Mask for channels > 5
7 EX External Mask
8-11 Key PSW key
12 A ASCII mode for decimal arithmetic
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-31 IC Interruption Code[5]
32-33 ILC Instruction-Length Code[6]
34-35 CC Condition Code
36-39 PM
Program Mask
Bit Meaning
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
40-63 IA Instruction Address
  • IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.

The System/360 architecture provides the following features:

Memory

Memory (storage) in System/360 is addressed in terms of 8-bit bytes. Various instructions operate on larger units called halfword (2 bytes), fullword (4 bytes), doubleword (8 bytes), quad word (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as big-endian. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term word refers to a fullword.

The original architecture of System/360 provided for up to 224 = 16,777,216 bytes of memory. The later Model 67 extended the architecture to allow up to 232 = 4,294,967,296[NB 1] bytes of virtual memory.

Addressing

System/360 uses truncated addressing similar to that of the UNIVAC III.[8] That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15[NB 2] general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.

Data formats

The S/360 architecture defines formats for characters, integers, decimal integers and hexadecimal floating point numbers. Character and integer instructions are mandatory, but decimal and floating point instructions are part of the Decimal arithmetic and Floating-point arithmetic features.

Instruction formats

Instructions in the S/360 are two, four or six bytes in length, with the opcode in byte 0. Instructions have one of the following formats:

Instructions must be on a two-byte boundary in memory; hence the low-order bit of the instruction address is always 0.

Program Status Word (PSW)

Main article: Program Status Word

The Program Status Word (PSW)[2]: 71–72  contains a variety of controls for the currently operating program. The 64-bit PSW describes (among other things) the address of the current instruction being executed, condition code and interrupt masks.

PSW format
Bits Contents Explanation
0-7 System Mask bits 0-5: enable channels 0-5, bit 6: enable all remaining channels,[NB 3] bit 7: enable External interruptions (timer, interrupt key, and external signal)PoOps: 71 
8-11 Protection key CPU protection key to compare against storage protection keys
12 ASCII mode enable ASCII mode for packed decimal instructions, never used by IBM software[NB 4]
13 Machine checks enable Machine check interruptions
14 Wait State processor is halted, an interruption, if enabled, will cause the processor to resume executing instructions
15 Problem state enable to prevent the use of instructions reserved for supervisor state
16-31 Interruption Code code to indicate the type of interruption, inserted when the PSW is stored, during IPLoad, this is the address of the device from which the program was loadedPoOps: 77 
32-33 Instruction Length Code length in halfwords or 0 if unavailable
34-35 Condition Code see individual instructions for encoding
36-39 Program Mask bit 36: enable fixed-point overflow, bit 37: decimal overflow, bit 38: exponent underflow, bit 39: significancePoOps: 71 
40-63 Instruction Address address of next instruction, except for a program interruptions with ILC 0

Load Program Status Word (LPSW) is a privileged instruction that loads the Program Status Word (PSW), including the program mode, protection key, and the address of the next instruction to be executed. LPSW is most often used to "return" from an interruption by loading the "old" PSW which is associated with the interruption class. Other privileged instructions (e.g., SSM, STNSM, STOSM, SPKA, etcetera) are available for manipulating subsets of the PSW without causing an interruption or loading a PSW; and one non-privileged instruction (SPM) is available for manipulating the program mask.

Interruption system

The architecture[2]: 77–83  defines 5 classes of interruption. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous[NB 5] and asynchronous events.

Interruption class Old PSW
hex dec
New PSW
hex dec
Priority
Input/OutputPoOps: 78–79  38   56 78  120 4
ProgramPoOps: 79–80.1  28   40 68 104 2
Supervisor CallPoOps: 80.1–81  20   32 60   96 2
ExternalPoOps: 81–82  18   24 58   88 3
Machine CheckPoOps: 82–83  30   48 70  112 1

There are two storage fields assigned to each class of interruption on the S/360; an old PSW double-word and a new PSW double-word. The processor stores the PSW, with an interruption code inserted, into the old PSW location and then loads the PSW from the new PSW location. This generally replaces the instruction address, thereby effecting a branch, and (optionally) sets and/or resets other fields within the PSW, thereby effecting a mode change.

The S/360 architecture defines a priority to each interruption class, but it is only relevant when two interruptions occur simultaneously; an interruption routine can be interrupted by any other enabled interruption, including another occurrence of the initial interruption. For this reason, it is normal practice to specify all of the mask bits, with the exception of machine-check mask bit, as 0 for the "first-level" interruption handlers. "Second-level" interruption handlers are generally designed for stacked interruptions (multiple occurrences of interruptions of the same interruption class).

Input/Output interruption

An I/O interruptionPoOps: 78–79  occurs at the completion of a channel program, after fetching a CCW with the PCI bit set and also for asynchronous events detected by the device, control unit or channel, e.g., completion of a mechanical movement. The system stores the device address into the interruption code and stores channel status into the CSW at location 64 ('40'X).

Program interruption

A Program interruption[2]: 16, 79–80.1  occurs when an instruction encounters one[NB 6] of 15[NB 7] exceptions; however, if the Program Mask bit corresponding to an exception is 0 then there is no interruption for that exception. On 360/65,[13]: 12  360/67[11]: 46  and 360/85[9]: 12  the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0. The Interruption code may be any of

Interruption codes for Program interruptions
old PSW bits 26-31
hex
bits 26-31
Dec Exception
0 0

Imprecise interruption[NB 6] on 360/91,[12]: 15  360/95 or 360/195[10]: 14 

1 1 OperationPoOps: 79 
2 2 Privileged operationPoOps: 79 
3 3 ExecutePoOps: 79 
4 4 ProtectionPoOps: 79 
5 5 AddressingPoOps: 79–80 
6 6 SpecificationPoOps: 80 
7 7 DataPoOps: 80 
8 8 Fixed-point overflowPoOps: 80 
9 9 Fixed-point dividePoOps: 80 
A 10 Decimal overflowPoOps: 80 
B 11 Decimal dividePoOps: 80 
C 12 Exponent overflowPoOps: 80 
D 13 Exponent underflowPoOps: 80 
E 14 SignificancePoOps: 80 
F 15 Floating-point dividePoOps: 80.1 
10 16

Segment Translation[11]: 17 [NB 7]

11 17

Page Translation[11]: 17 [NB 7]

12 18

SSM Exception[13][NB 7]

Supervisor Call interruption

A Supervisor Call interruptionPoOps: 80.1–81  occurs as the result of a Supervisor Call instruction; the system stores bits 8-15 of the SVC instruction as the Interruption Code.

External interruption

An ExternalPoOps: 81 [NB 11] interruption occurs as the result of certain asynchronous events. Bits 16-24 of the External Old PSW are set to 0 and one or more of bits 24-31 is set to 1

Interruption codes for External interruptions
PSW bit Type of external interruption

24

Timer

25

Interrupt key

26

External signal 2
Malfunction alert on 360/65[13] in Multisystem mode

27

External signal 3
System Call on 360/65[13] in Multisystem mode

28

External signal 4

29

External signal 5

30

External signal 6

31

External signal 7

Machine Check interruption

A Machine Check interruptionPoOps: 82–83  occurs to report unusual conditions associated with the channel or CPU that cannot be reported by another class of interruption. The most important class of conditions causing a Machine Check is a hardware error such as a parity error found in registers or storage, but some models may use it to report less serious conditions. Both the interruption code and the data stored in the scanout area at '80'x (128 decimal) are model dependent.

Input/Output

This article describes I/O from the CPU perspective. It does not discuss the channel cable or connectors, but there is a summary elsewhere and details can be found in the IBM literature.[3]

I/O is carried out by a conceptually separate processor called a channel. Channels have their own instruction set, and access memory independently of the program running on the CPU. On the smaller models (through 360/50) a single microcode engine runs both the CPU program and the channel program. On the larger models the channels are in separate cabinets and have their own interfaces to memory. A channel may contain multiple subchannels, each containing the status of an individual channel program. A subchannel associated with multiple devices that cannot concurrently have channel programs is referred to as shared; a subchannel representing a single device is referred to as unshared.

There are three types of channels on the S/360:

Conceptually peripheral equipment is attached to a S/360 through control units, which in turn are attached through channels. However, the architecture does not require that control units be physically distinct, and in practice they are sometimes integrated with the devices that they control. Similarly, the architecture does not require the channels to be physically distinct from the processor, and the smaller S/360 models (through 360/50) have integrated channels that steal cycles from the processor.

Peripheral devices are addressed with 16-bit[NB 12] addresses.,[2]: 89  referred to as cua or cuu; this article will use the term cuu. The high 8 bits identify a channel, numbered from 0 to 6,[NB 3] while the low 8 bits identify a device on that channel. A device may have multiple cuu addresses.

Control units are assigned an address "capture" range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, a channel might have three disk control units at 20-2F, 50-5F, and 80-8F. Not all of the captured addresses need to have an assigned physical device. Each control unit is also marked as High or Low priority on the channel.

Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain the selection process continues in reverse back towards the channel. If the selection returns to the channel then no control unit accepted the command and SIO returns Condition Code 3. Control units marked as High Priority check the outbound CUU to be within their range. If so, then the I/O was processed. If not, then the selection was passed to the next outbound CU. Control units marked as Low Priority check for inbound (returning) CUU to be within their range. If so, then the I/O is processed. If not, then the selection is passed to the next inbound CU (or the channel). The connection of three controls unit to a channel might be physically -A-B-C and, if all are marked as High then the priority would be ABC. If all are marked low then the priority would be CBA. If B was marked High and AC low then the order would be BCA. Extending this line of reasoning then the first of N controllers would be priority 1 (High) or 2N-1 (Low), the second priority 2 or 2N-2, the third priority 3 or 2N-3, etc. The last physically attached would always be priority N.

There are three storage fields reserved for I/O; a double word I/O old PSW, a doubleword I/O new PSW and a fullword Channel Address Word (CAW). Performing an I/O normally requires the following:

A channel program consists of a sequence of Channel Control Words (CCWs) chained together (see below.) Normally the channel fetches CCWs from consecutive doublewords, but a control unit can direct the channel to skip a CCW and a Transfer In Channel (TIC) CCW can direct the channel to start fetching CCWs from a new location.

There are several defined ways for a channel command to complete. Some of these allow the channel to continue fetching CCWs, while others terminate the channel program. In general, if the CCW does not have the chain-command bit set and is not a TIC, then the channel will terminate the I/O operation and cause an I/O interruption when the command completes. Certain status bits from the control unit suppress chaining.

The most common ways for a command to complete are for the count to be exhausted when chain-data is not set and for the control unit to signal that no more data transfers should be made. If Suppress-Length-Indication (SLI) is not set and one of those occurs without the other, chaining is not allowed. The most common situations that suppress chaining are unit-exception and unit-check. However, the combination of unit-check and status-modifier does not suppress chaining; rather, it causes the channel to do a command retry, reprocessing the same CCW.

In addition to the interruption signal sent to the CPU when an I/O operation is complete, a channel can also send a Program-Controlled interruption (PCI) to the CPU while the channel program is running, without terminating the operation, and a delayed device-end interruption after the I/O completion interruption.

Channel status

These conditions are detected by the channel and indicated in the CSW.PoOps: 116–118 

Unit status

These conditions are presented to the channel by the control unit or device.PoOps: 113–116  In some cases they are handled by the channel and in other cases they are indicated in the CSW. There is no distinction between conditions detected by the control unit and conditions detected by the device.

A typical channel program where SM occurs is
    ...
    Search Id Equal
    TIC           *-8
    Read Data
where the TIC causes the channel to refetch the search until the device indicates a successful search by raising SM.

Channel Address Word

The fullword Channel Address Word[2]: 99  (CAW) contains a 4-bit storage protection key and a 24-bit address of the channel program to be started.

Channel Command Word

A Channel Command Word is a doubleword containing the following:

CCW Command codes

The low order 2 or 4 bits determine the six types of operations that the channel performs;.[2]: 100, 105  The encoding is

CCW Command codes
bits Command
**** 0000 Invalid in a CCW, simulated by the processor's Test I/O (TIO) instruction
MMMM 0100 SensePoOps: 106–107 
**** 1000 Transfer in Channel (TIC)PoOps: 107–108 
MMMM 1100 Read BackwardPoOps: 105–106 
MMMM MM01 WritePoOps: 105 
MMMM MM10 ReadPoOps: 105 
MMMM MM11 ControlPoOps: 106–107 

The meaning of the high order six or four bits, the modifier bits, M in the table above, depends upon the type of I/O device attached, see e.g., DASD CKD CCWs. All eight bits are sent to and interpreted in the associated control unit (or its functional equivalent).

Control is used to cause a state change in a device or control unit, often associated with mechanical motion, e.g., rewind, seek.

Sense is used to read data describing the status of the device. The most important case is that when a command terminates with unit check, the specific cause can only be determined by doing a Sense and examining the data returned. A Sense command with the modifier bits all zero is always valid.

A noteworthy deviation from the architecture is that DASD use Sense command codes for Reserve and Release, instead of using Control.

CCW flags

The flags in a CCW affect how it executes and terminates.

CCW flags
bit flag effect
32 CD Chain-Data Continue operation using the storage area defined by the next CCW.PoOps: 101–103 
33 CC Chain-Command Continue with the Command in the next CCW.PoOps: 101, 103 
34 SLI[NB 15] Suppress-Length-Indication Continue channel program after count mis-match.PoOps: 99–100 
35 SKIP Skip Do not read from or write into storage.PoOps: 103–104 
36 PCI Program-Controlled-Interruption Request interruption when fetching CCW.PoOps: 104–105 

Channel Status Word

The Channel Status Word (CSW)[2]: 113–121  provides data associated with an I/O interruption.

CSW format
bits field
0-3 KeyPoOps: 119 
4-7 0000
8-31 Command AddressPoOps: 119 
32-47 StatusPoOps: 113–118 
32-39
Unit Status ConditionsPoOps: 113–116 
Detected by the device or control unit
32
AttentionPoOps: 113 
33
Status modifierPoOps: 113–114 
34
Control unit endPoOps: 114 
35
BusyPoOps: 114–115 
36
Channel endPoOps: 115 
37
Device endPoOps: 115 
38
Unit checkPoOps: 115–116 
39
Unit exceptionPoOps: 116 
40-47
Channel Status ConditionsPoOps: 116–118 
Detected by the channel.
40
Program-controlled interruptionPoOps: 116–117 
41
Incorrect lengthPoOps: 117 
42
Program checkPoOps: 117 
43
Protection checkPoOps: 117–118 
44
Channel data checkPoOps: 118 
45
Channel control checkPoOps: 118 
46
Interface control checkPoOps: 118 
47
Chaining checkPoOps: 118 
48-63 CountPoOps: 120 

Operator controls

operator controls
operator controls

The architecture of System/360 specified the existence of several common functions, but did not specify their means of implementation. This allowed IBM to use different physical means, e.g., dial, keyboard, pushbutton, roller, image or text on a CRT, for selecting the functions and values on different processors. Any reference to key or switch should be read as applying to, e.g., a light-pen selection, an equivalent keyboard sequence.

As part of the IPL facility the operator has a means of specifying a 12-bit[NB 3] device address, typically with three dials as shown in the operator controls drawing. When the operator[NB 16] selects the Load function, the system performs a System Reset, sends a Read IPL[NB 17] channel command to the selected device in order to read 24 bytes into locations 0-23 and causes the channel to begin fetching CCWs at location 8; the effect is as if the channel had fetched a CCW with a length of 24, and address of 0 and the flags containing Command Chaining + Suppress Length Indication. At the completion of the operation, the system stores the I/O address in the halfword at location 2 and loads the PSW from location 0.
Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for installing an operating system on a new computer.

Optional features

Byte-aligned operands

On some models the alignment requirements for some problem-state instructions were relaxed. There is no mechanism to turn off this feature, and programs depending on receiving a program check type 6 (alignment) on those instructions must be modified.

Decimal arithmetic

The decimal arithmetic feature provides instructions that operate on packed decimal data. A packed decimal number has 1-31 decimal digits followed by a 4-bit sign. All of the decimal arithmetic instructions except PACK and UNPACK generate a Data exception if a digit is not in the range 0-9 or a sign is not in the range A-F.

Direct Control

The Direct ControlPoOps: 17.1  feature provides six external signal lines and an 8-bit data path to/from storage.[14]

Floating-point arithmetic

The floating-point arithmetic feature provides 4 64-bit floating point registers and instructions to operate on 32 and 64 bit hexadecimal floating point numbers. The 360/85 and 360/195 also support 128 bit extended precision floating point numbers.

Interval timer

If the interval timer feature[2]: 17.1  is installed, the processor decrements the word at location 80 ('50'X) at regular intervals; the architecture does not specify the interval but does require that value subtracted make it appear as though 1 were subtracted from bit 23 300 times per second. The smaller models decremented at the same frequency (50 Hz or 60 Hz) as the AC power supply, but larger models had a high resolution timer feature. The processor causes an External interruption when the timer goes to zero.

Multi-system operation

Multi-system operationPoOps: 17.1–18  is a set of features to support multi-processor systems, e.g., Direct Control, direct address relocation (prefixing).

Storage protection

If the storage protection feature[2]: 17-17.1  is installed, then there is a 4-bit storage key associated with every 2,048-byte block of storage and that key is checked when storing into any address in that block by either a CPU or an I/O channel. A CPU or channel key of 0 disables the check; a nonzero CPU or channel key allows data to be stored only in a block with the matching key.

Storage Protection was used to prevent a defective application from writing over storage belonging to the operating system or another application. This permitted testing to be performed along with production. Because the key was only four bits in length, the maximum number of different applications that could be run simultaneously was 15.

An additional option available on some models was fetch protection. It allowed the operating system to specify that blocks were protected from fetching as well as from storing.

Deviations and extensions

The System/360 Model 20 is radically different and should not be considered to be a S/360.

The System/360 Model 44 is missing certain instructions, but a feature allowed the missing instructions to be simulated in hidden memory thus allowing the use of standard S/360 operating systems and applications.

Some models have features that extended the architecture, e.g., emulation instructions, paging, and some models make minor deviations from the architecture. Examples include:

Some deviations served as prototypes for features of the S/370 architecture.

See also

Notes

  1. ^ Twice the size of the later System/370
  2. ^ A specification of general register 0 yield a base address of zero rather than the register content.
  3. ^ a b c On a processor that complies with the S/360 architecture, the highest channel number is 6. Eleven bits are sufficient to identify the cuu, and seven bits are sufficient to provide masking of I/O interruptions. However, on a 360/67-2 with two 2846 channel controllers, channels are numbered 0-6 and 8-14;[11]: 15  similarly, the 360/195 had an extended channel feature[10]: 21  but numbered the channels 0 through 13.[10]: 25  I/O interruptions for Channel Controller 1 on the 360/67-2 were masked using control registers, and the 360/195 used bit 7 (Channel 6) of the System Mask as a summary mask bit for channels 6 and up. Interruptions from More than Seven ChannelsPoOps: 121.4  describes the summary masking for additional channels, but other text in Principles of Operation still refers to a limit of 7 channels. Standard software supported channels 0-F.
  4. ^ Because the design of the S/360 occurred simultaneously with the development of ASCII, IBM's ASCII support did not match the standard that was ultimately adopted.
  5. ^ The S/360 literature does not use the terms fault or trap
  6. ^ a b On the 360/91,[12]: 15  360/95 and 360/195[10]: 14  a Program interruption may occur for multiple imprecise exceptions. The ILC in the Program Old PSW is 0, bits 26-31 are 0 and bits 16-27 are a mask indicating which exceptions occurred; there is no provision for reporting multiple occurrences of the same exception. Reporting of multiple imprecise exceptions is not part of the S/360 architecture.
  7. ^ a b c d There are 17 possible exceptions on the 360/67,[11]: 17  but page exception and segment exception are not part of the S/360 architecture; similarly, interruption code 18 ('0012'X) on a 360/65 multiprocessor is not part of the S/360 architecture.
  8. ^ The Specification bit is not used for imprecise interruptions on the 360/195
  9. ^ a b Not Used on 360/91
  10. ^ A PSW key of 0 matches any storage key.
  11. ^ Even though a timer expiration is an internal event, it causes an External interruption and for this reason, this interruption is usually referred to as a timer/external interruption.
  12. ^ Because of the limits on the channel number, S/360 and early S/370 software only used 12 bits to store device addresses.
  13. ^ But continuing with unrelated work.
  14. ^ The OS uses the attention index in a Unit Control Block (UCB) as an index into the attention table.
  15. ^ Also known as Suppress Incorrect Length Indication (SILI)
  16. ^ Or an equivalent automated facility.
  17. ^ Read with all modifier bits zero
  18. ^ There is an inconsistency, in that Interruptions from More than Seven ChannelsPoOps: 121.4  allows for more channels.

References

S360
IBM System/360 Principles of Operation. Systems Reference Library (Eighth ed.). IBM. September 1968. A22-6821-7.
  1. ^ IBM (1964), IBM System/360 Principles of Operation (PDF), First Edition, A22-6821-0
  2. ^ a b c d e f g h i j k IBM (September 1968), IBM System/360 Principles of Operation (PDF), Eighth Edition, A22-6821-7 Revised by IBM (May 12, 1970), ibid., GN22-0354 and IBM (June 8, 1970), ibid., GN22-0361
  3. ^ a b IBM, IBM System/360 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information (PDF), Fifth Edition, A22-6843-3
  4. ^ S360, p. 15, Program Status Word.
  5. ^ S360, pp. 15 –&#32, 16, Interruption.
  6. ^ S360, p. 77, Interruptions.
  7. ^ IBM Corporation (1974). IBM System/360 System Summary (PDF). p. 3-3. Retrieved July 16, 2017.
  8. ^ Reference Manual UNIVAC III Data Processing System (PDF), Sperry Rand Corporation, 1962, UT-2488
  9. ^ a b IBM (June 1968), IBM System/360 Model 85 Functional Characteristics (PDF), SECOND EDITION, A22-6916-1
  10. ^ a b c d e IBM (August 1970), IBM System/360 Model 195 Functional Characteristics (PDF), Second Edition, GA22-6943-1
  11. ^ a b c d e f IBM (February 1972), IBM System/360 Model 67 Functional Characteristics (PDF), Third Edition, GA27-2719-2
  12. ^ a b IBM (1968-03-18), IBM System/360 Model 91 Functional Characteristics (PDF), Third Edition, A22-6907-2
  13. ^ a b c d e IBM (September 1968), "Appendix A. Multiprocessing System", IBM System/360 Model 65 Functional Characteristics (PDF), Fourth Edition, pp. 30–34, A22-6884-3
  14. ^ IBM, IBM System/360 Direct Control and External Interrupt Features Original Equipment Manufacturers' Information (PDF), Third Edition, A22-6845-2

Further reading