A processor register is a quickly accessible location available to a computer's processor. Registers usually consist of a small amount of fast storage, although some registers have specific hardware functions, and may be read-only or write-only. In computer architecture, registers are typically addressed by mechanisms other than main memory, but may in some cases be assigned a memory address e.g. DEC PDP-10, ICT 1900.
Almost all computers, whether load/store architecture or not, load data from a larger memory into registers where it is used for arithmetic operations and is manipulated or tested by machine instructions. Manipulated data is then often stored back to main memory, either by the same instruction or by a subsequent one. Modern processors use either static or dynamic RAM as main memory, with the latter usually accessed via one or more cache levels.
Processor registers are normally at the top of the memory hierarchy, and provide the fastest way to access data. The term normally refers only to the group of registers that are directly encoded as part of an instruction, as defined by the instruction set. However, modern high-performance CPUs often have duplicates of these "architectural registers" in order to improve performance via register renaming, allowing parallel and speculative execution. Modern x86 design acquired these techniques around 1995 with the releases of Pentium Pro, Cyrix 6x86, Nx586, and AMD K5.
When a computer program accesses the same data repeatedly, this is called locality of reference. Holding frequently used values in registers can be critical to a program's performance. Register allocation is performed either by a compiler in the code generation phase, or manually by an assembly language programmer.
Registers are normally measured by the number of bits they can hold, for example, an "8-bit register", "32-bit register" or a "64-bit register" or even more. In some instruction sets, the registers can operate in various modes breaking down its storage memory into smaller ones (32-bit into four 8-bit ones for instance) to which multiple data (vector, or one dimensional array of data) can be loaded and operated upon at the same time. Typically it is implemented by adding extra registers that map their memory into a larger register. Processors that have the ability to execute single instructions on multiple data are called vector processors.
A processor often contains several kinds of registers, which can be classified according to their content or instructions that operate on them:
Hardware registers are similar, but occur outside CPUs.
In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten. In Alpha this is also done for the floating-point register file. As a result of this, register files are commonly quoted as having one register more than how many of them are actually usable; for example, 32 registers are quoted when only 31 of them fit within the above definition of a register.
The following table shows the number of registers in several mainstream CPU architectures. Note that in x86-compatible processors the stack pointer (
ESP) is counted as an integer register, even though there are a limited number of instructions that may be used to operate on its contents. Similar caveats apply to most architectures.
Although all of the above-listed architectures are different, almost all are in a basic arrangement known as the von Neumann architecture, first proposed by the Hungarian-American mathematician John von Neumann. It is also noteworthy that the number of registers on GPUs is much higher than that on CPUs.
|Architecture||GPRs/data+address registers||FP registers||Notes|
|AT&T Hobbit||0||stack of 7||All data manipulation instructions work solely within registers, and data must be moved into a register before processing.|
|Cray-1||8 scalar data, 8 address||8 scalar, 8 vector
|Scalar data registers can be integer or floating-point; also 64 scalar scratch-pad T registers and 64 address scratch-pad B registers|
|4004||1 accumulator, 16 others||0||Register A is general-purpose, while the r0–r15 registers are for the address and segment.|
|8008||1 accumulator, 6 others||0||The A register is an accumulator to which all arithmetic is done; the H and L registers can be used in combination as an address register; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. There is no FP unit available.|
|8080||1 accumulator, 6 others||0||Plus a stack pointer. The A register is an accumulator to which all arithmetic is done; the register pairs B+C, D+E, and H+L can be used as address registers in some instructions; all registers can be used as operands in load/store/move/increment/decrement instructions and as the other operand in arithmetic instructions. Some instructions only use H+L; another instruction swaps H+L and D+E. Floating point processors intended for the 8080 were Intel 8231, AMD Am9511 and Intel 8232. They were also readily usable with the Z80 and similar processors.|
|iAPX432||0||stack of 6||Stack machine|
|16-bit x86||6||stack of 8
(if FP present)
|8086/8088, 80186/80188, 80286, with 8087, 80187 or 80287 for floating-point, with an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands; without 8087/80187/80287, no floating-point registers|
|IA-32||8||stack of 8 (if FP present),
8 (if SSE/MMX present)
|80386 required 80387 for floating-point, later processors had built-in floating point, with both having an 80-bit wide, 8 deep register stack with some instructions able to use registers relative to the top of the stack as operands. The Pentium III and later had the SSE with additional 128-bit XMM registers.|
|x86-64||16||16 or 32
(if AVX-512 available)
|FP registers are 128-bit XMM registers, later extended to 256-bit YMM registers with AVX/AVX2 and 512-bit ZMM0–ZMM31 registers with AVX-512.|
|Fairchild F8||one accumulator, 64 scratchpad registers, one indirect scratchpad register (ISAR)||—||Instructions can directly reference the first 16 scratchpad registers and can access all scratchpad registers indirectly through the ISAR|
|Geode GX||1 data, 1 address||8||Geode GX/Media GX/4x86/5x86 is the emulation of 486/Pentium compatible processor made by Cyrix/National Semiconductor. Like Transmeta, the processor had a translation layer that translated x86 code to native code and executed it. It does not support 128-bit SSE registers, just the 80387 stack of eight 80-bit floating point registers, and partially supports 3DNow! from AMD. The native processor only contains 1 data and 1 address register for all purposes and it is translated into 4 paths of 32-bit naming registers r1 (base), r2 (data), r3 (back pointer), and r4 (stack pointer) within scratchpad SRAM for integer operation and it uses the L1 cache for x86 code emulation (it's not compatible with some 286/386/486 instructions in real mode). Later the design was abandoned after AMD acquired the IP from National Semiconductor and branded it with Athlon core in embedded market.|
|SunPlus SPG||0||6 stack + 4 SIMD||A 16-bit wide, 32-bit address space stack machine processor from the Taiwanese company Sunplus Technology, it can be found on Vtech's V.Smile line for educational purposes and video game consoles such as the Wireless 60, Mattel HyperScan, and XaviXPORT. It lacks any general-purpose register or internal register for naming/renaming but its Floating Point Unit has an 80-bit 6 stage stack and four 128-bit VLIW SIMD registers on a vertex shader co-processor.|
|VM Labs Nuon||0||1||A 32-bit stack machine processor developed by VM Labs and specialized for multimedia. It can be found on the company's own Nuon DVD player console line and the Game Wave Family Entertainment System from ZaPit games. The design was heavily influenced by Intel's MMX technology; it contained a 128-byte unified stack cache for both vector and scalar instructions. The unified cache can be divided as 8 128-bit vector registers or 32 32-bit SIMD scalar registers through bank renaming; there is no integer register in this architecture.|
|Nios II||31||8||Nios II is based on the MIPS IV instruction set and has 31 32-bit GPRs, with register 0 being hardwired to zero, and 8 64-bit floating point registers|
|Motorola 6800||2 data, 1 index||0||Plus a stack pointer|
|Motorola 68k||8 data (d0–d7), 8 address (a0–a7)||
(if FP present)
|Address register 8 (a7) is the stack pointer. 68000, 68010, 68012, 68020, and 68030 require an FPU for floating point; 68040 had FPU built in. FP registers are 80-bit.|
|Emotion Engine||3(VU0)+ 32(VU1)||32 SIMD (integrated in UV1)
+ 2 × 32 Vector (dedicated vector co-processor that located near by its GPU)
|The Emotion Engine's main core (VU0) is a heavily modified DSP general core intended for general background tasks and it contains one 64-bit accumulator, two general data registers, and one 32-bit program counter. A modified MIPS III executable core(VU1) is for game data and protocol control and it contains 32 32-bit general-purpose registers for integer computation and 32 128-bit SIMD registers for storing SIMD instructions, streaming data value and some integer calculation value, and one accumulator register for connecting general floating-point computation to the vector register file on the co-processor. The coprocessor is built via a 32-entry 128-bit vector register file (can only store vector values that pass from the accumulator in the CPU) and no integer registers are built in. Both the vector co-processor(VPU 0/1) and the Emotion Engine's entire main processor module(VU0 + VU1 + VPU0 + VPU1) are built based on a modified MIPS instructions set. The accumulator in this case is not general purpose but control status.|
|CUDA||configurable, up to 255 per thread||Earlier generations allowed up to 127/63 registers per thread (Tesla/Fermi). The more registers are configured per thread, the fewer threads can run at the same time. Registers are 32 bits wide, double precision floating point numbers and 64 bit pointers therefore require two registers. It additionally has up to 8 predicate registers per thread.|
|CDC 6000 series||16||8||8 'A' registers, A0–A7, hold 18-bit addresses; 8 'B' registers, B0–B7, hold 18-bit integer values (with B0 permanently set to zero); 8 'X' registers, X0–X7, hold 60 bits of integer or floating-point data. Seven of the eight 18-bit A registers were coupled to their corresponding X registers: setting any of the A1–A5 registers to a value caused a memory load of the contents of that address into the corresponding X register. Likewise, setting an address into registers A6 or A7 caused a memory store into that location in memory from X6 or X7. (Registers A0 and X0 were not coupled like this).|
|System/360, System/370, System/390, z/Architecture||16||4 (if FP present);
16 in G5 and later S/390 models and z/Architecture
|FP was optional in System/360, and always present in S/370 and later. In processors with the Vector Facility, there are 16 vector registers containing a machine-dependent number of 32-bit elements. Some registers are assigned a fixed purpose by calling conventions; for example, register 14 is used for subroutine return addresses and, for ELF ABIs, register 15 is used as a stack pointer. The S/390 G5 processor increased the number of floating-point registers to 16.|
|MMIX||256||256||An instruction set designed by Donald Knuth in the late 1990s for pedagogical purposes.|
(if FP present)
|Xelerated X10||1||32||A 32/40-bit stack machine based network processor with a modified MIPS instruction set and a 128 bit floating point unit.|
|Parallax Propeller||0||2||An 8 core 8/16 bit sliced stack machine controller with a simple logic circuit inside, it has 8 cog counters (cores), each containing three 8/16 bit special control registers with 32 bit x 512 stack RAM. However, it does not contain any general register for integer purposes. Unlike most shadow register files in modern processors and multi core systems, all of the stack RAM in cog can be accessed in instruction level which allows all of these cogs to act as a single general purpose core if necessary. Floating point unit is external and it contains two 80 bit vector registers.|
|Itanium||128||128||And 64 1-bit predicate registers and 8 branch registers. The FP registers are 82-bit.|
|SPARC||31||32||Global register 0 is hardwired to 0. Uses register windows.|
|IBM POWER||32||32||And 1 link and 1 count register.|
|Power ISA||32||32||And 1 link and 1 count register. Processors supporting the Vector facility also have 32 128-bit vector registers.|
|Blackfin||8 data, 2 accumulator, 6 address||0||And stack pointer and frame pointer. Additional registers are used to implement zero-overhead loops and circular buffer DAGs (data address generators).|
|IBM Cell SPE||128||128 GPRs, which can hold integer, address, or floating-point values|
|PDP-10||16||All of the registers may be used generally (integer, float, stack pointer, jump, indexing, etc.). Every 36-bit memory (or register) word can also be manipulated as a half-word, which can be considered an (18-bit) address. Other word interpretations are used by certain instructions. In the original PDP-10 processors, these 16 GPRs also corresponded to main (i.e. core) memory locations 0–15; a hardware option called "fast memory" implemented the registers as separate ICs, and references to memory locations 0–15 referred to the IC registers. Later models implemented the registers as "fast memory" and continued to make memory locations 0–15 refer to them. Movement instructions take (register, memory) operands: |
(if FPP present)
|R7 is the program counter. Any register can be a stack pointer but R6 is used for hardware interrupts and traps.|
|VAX||16||The GPRs are used for floating-point values as well. Three of the registers have special uses: R12 (Argument Pointer), R13 (Frame Pointer), and R14 (Stack Pointer), while R15 refers to the Program Counter.|
|Alpha||31||31||Registers R31 (integer) and F31 (floating-point) are hardwired to zero.|
|6502||1 data, 2 index||0||6502's content A (Accumulator) register for main purpose data store and memory address (8-bit data/16-bit address), X,Y are indirect and direct index registers (respectively) and the SP registers are specific index only.|
|W65C816S||1||0||65c816 is the 16-bit successor of the 6502. X,Y, D (Direct Page register) are condition registers and SP register are specific index only. Main accumulator extended to 16-bit (C) while keeping 8-bit (A) for compatibility and main registers can now address up to 24-bit (16-bit wide data instruction/24-bit memory address).|
|MeP||4||8||Media-embedded processor was a 32 bit processor developed by Toshiba with a modded 8080 instruction set with only the A, B, C, and D registers available through all modes (8/16/32 bit). It is incompatible with x86; however, it contains a 80 bit floating point unit that is x87 compatible.|
|ARM 32-bit (ARM/A32, Thumb-2/T32)||14||Varies
(up to 32)
|r15 is the program counter, and not usable as a GPR; r13 is the stack pointer; r8–r13 can be switched out for others (banked) on a processor mode switch. Older versions had 26-bit addressing, and used upper bits of the program counter (r15) for status flags, making that register 32-bit.|
|ARM 32-bit (Thumb)||8||16||Version 1 of Thumb, which only supported access to registers r0 through r7|
|ARM 64-bit (A64)||31||32||Register r31 is the stack pointer or hardwired to 0, depending on the context.|
|MIPS||31||32||Integer register 0 is hardwired to 0.|
|RISC-V||31||32||Integer register 0 hardwired to 0. The variant RV32E intended for systems with very limited resources has 15 integer registers.|
|Epiphany||64 (per core)||Each instruction controls whether registers are interpreted as integers or single precision floating point. Architecture is scalable to 4096 cores with 16 and 64 core implementations currently available.|
The number of registers available on a processor and the operations that can be performed using those registers has a significant impact on the efficiency of code generated by optimizing compilers. The Strahler number of an expression tree gives the minimum number of registers required to evaluate that expression tree.