|Computer architecture bit widths|
|Binary floating-point precision|
|Decimal floating-point precision|
In computer architecture, 256-bit integers, memory addresses, or other data units are those that are 256 bits (32 octets) wide. Also, 256-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers, address buses, or data buses of that size. There are currently no mainstream general-purpose processors built to operate on 256-bit integers or addresses, though a number of processors do operate on 256-bit data.
A 256-bit register can store 2256 different values. The range of integer values that can be stored in 256 bits depends on the integer representation used.
The maximum value of an unsigned 256-bit integer is 2256 − 1, written in decimal as 115,792,089,237,316,195,423,570,985,008,687,907,853,269,984,665,640,564,039,457,584,007,913,129,639,935 or approximately as 1.1579 x 1077.
256-bit processors could be used for addressing directly up to 2256 bytes. Already 2128 (for 128-bit addressing) would greatly exceed the total data stored on Earth as of 2018, which has been estimated to be around 33.3 zettabytes (over 275 bytes).
Xbox 360 was the first high-definition gaming console to utilize the ATI Technologies 256-bit GPU Xenos before the introduction of the current gaming consoles especially Nintendo Switch.
Some buses on the newer System on a chip (e.g. Tegra developed by Nvidia) utilize 64-bit, 128-bit, 256-bit, or higher.
CPUs feature SIMD instruction sets (Advanced Vector Extensions and the FMA instruction set etc.) where 256-bit vector registers are used to store several smaller numbers, such as eight 32-bit floating-point numbers, and a single instruction can operate on all these values in parallel. However, these processors do not operate on individual numbers that are 256 binary digits in length, only their registers have the size of 256-bits. Binary digits are found together in 128-bit collections.
Modern GPU chips may operate data across a 256-bit memory bus (or possibly a 512-bit bus with HBM3).
The Efficeon processor was Transmeta's second-generation 256-bit VLIW design which employed a software engine to convert code written for x86 processors to the native instruction set of the chip.
The DARPA funded Data-Intensive Architecture (DIVA) system incorporated processor-in-memory (PIM) 5-stage pipelined 256-bit datapath, complete with register file and ALU blocks in a "WideWord" processor in 2002.