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Closeup of the pins of a pin grid array
The pin grid array at the bottom of a XC68020, a prototype of the Motorola 68020 microprocessor
The pin grid array on the bottom of an AMD Phenom X4 9750 processor that uses the AMD AM2+ socket

A pin grid array (PGA) is a type of integrated circuit packaging. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,[1] and may or may not cover the entire underside of the package.

PGAs are often mounted on printed circuit boards using the through hole method or inserted into a socket. PGAs allow for more pins per integrated circuit than older packages, such as dual in-line package (DIP).

Chip mounting

Underside of an 80486 with lid removed shows die and wire bonded connections.

The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either by wire bonding or through flip chip mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for example Zen 2 and Zen 3 Ryzen CPUs for the AM4 socket.

Flip chip

The underside of a FC-PGA package (The die is on the other side.)

A flip-chip pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the die faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the heatsink or other cooling mechanism.

FC-PGA CPUs were introduced by Intel in 1999, for Coppermine core Pentium III and Celeron[2] processors based on Socket 370, and were produced until Socket G3 in 2013. FC-PGA processors fit into zero insertion force (ZIF) motherboard sockets; similar packages were also used by AMD.



A ceramic pin grid array (CPGA) is a type of packaging used by integrated circuits. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some CPUs that use CPGA packaging are the AMD Socket A Athlons and the Duron.

A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on Socket AM2 and Socket AM2+. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a ceramic substrate with pins arranged in an array.


Demonstration of a PGA-ZIF socket (AMD 754)

An organic pin grid array (OPGA) is a type of connection for integrated circuits, and especially CPUs, where the silicon die is attached to a plate made out of an organic plastic which is pierced by an array of pins which make the requisite connections to the socket.


The topside of a Celeron-400 in a PPGA packing

Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino core Celeron processors based on Socket 370.[3] Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.

Underside of a Pentium 4 in a PGA package

Pin layout

Staggered pin

The staggered pin grid array (SPGA) is used by Intel processors based on Socket 5 and Socket 7. Socket 8 used a partial SPGA layout on half the processor.

An example of a socket for a staggered pin grid array package
View of the socket 7 321-pin connectors of a CPU

It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square lattice. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as microprocessors.


A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in surface-mount technology. The polymer stud grid array or plastic stud grid array was developed jointly by the Interuniversity Microelectronics Centre (IMEC) and Laboratory for Production Technology, Siemens AG.[4][5]


The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1 mm,[6] as opposed to the 1.27 mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the G1, G2, and G3 sockets.

See also


  1. ^ Vijay Nath (24 March 2017). Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems. Springer. p. 304. ISBN 978-981-10-2999-8.
  2. ^ "Intel Releases New Design for sub-$1,000 PCs". Philippine Daily Inquirer. April 24, 2000. ((cite web)): Missing or empty |url= (help)
  3. ^ Robert Bruce Thompson; Barbara Fritchman Thompson (24 July 2003). PC Hardware in a Nutshell: A Desktop Quick Reference. O'Reilly Media, Inc. p. 44. ISBN 978-0-596-55234-3.
  4. ^ "BGA socket/BGA 소켓". Retrieved 2015-06-05.
  5. ^ link (in German) Archived October 1, 2011, at the Wayback Machine
  6. ^ "Molex Sockets for Servers, Desktops and Notebooks Earn Intel® Validation". Archived from the original on 2019-12-09. Retrieved 2016-03-15.