This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed.Find sources: "System in a package" – news · newspapers · books · scholar · JSTOR (February 2014) (Learn how and when to remove this message)
CAD drawing of a SiP multi-chip which contains a processor, memory and storage on a single substrate

A system in a package (SiP) or system-in-package is a number of integrated circuits (ICs) enclosed in one chip carrier package or encompassing an IC package substrate that may include passive components and perform the functions of an entire system. The ICs may be stacked using package on package, placed side by side, and/or embedded in the substrate.[1] The SiP performs all or most of the functions of an electronic system, and is typically used when designing components for mobile phones, digital music players, etc.[2] Dies containing integrated circuits may be stacked vertically on the package substrate. They are internally connected by fine wires that are bonded to the package substrate. Alternatively, with a flip chip technology, solder bumps are used to join stacked chips together and to the package substrate, or even both techniques can be used in a single package. SiPs are like systems on a chip (SoCs) but less tightly integrated and not on a single semiconductor die.[3]

SIPs can be used either to reduce the size of a system, improve performance or to reduce costs.[4][5] The technology evolved from multi chip module (MCM) technology, the difference being that SiPs also use die stacking, which stacks several chips or dies on top of each other.[6][7]


SiP dies can be stacked vertically or tiled horizontally, with techniques like chiplets or quilt packaging. SiPs connect the dies with standard off-chip wire bonds or solder bumps, unlike slightly denser three-dimensional integrated circuits which connect stacked silicon dies with conductors running through the die using through-silicon vias. Many different 3D packaging techniques have been developed for stacking many fairly standard chip dies into a compact area.[8]

SiPs can contain several chips or dies—such as a specialized processor, DRAM, flash memory—combined with passive componentsresistors and capacitors—all mounted on the same substrate. This means that a complete functional unit can be built in a single package, so that few external components need to be added to make it work. This is particularly valuable in space constrained environments like MP3 players and mobile phones as it reduces the complexity of the printed circuit board and overall design. Despite its benefits, this technique decreases the yield of fabrication since any defective chip in the package will result in a non-functional packaged integrated circuit, even if all other modules in that same package are functional.

SiPs are in contrast to the common system on a chip (SoC) integrated circuit architecture which integrates components based on function into a single circuit die. An SoC will typically integrate a CPU, graphics and memory interfaces, hard-disk and USB connectivity, random-access and read-only memories, and secondary storage and/or their controllers on a single die. In comparison an SiP would connect these modules as discrete components in one or more chip packages or dies. An SiP resembles the common traditional motherboard-based PC architecture, as it separates components based on function and connects them through a central interfacing circuit board. An SiP has a lower grade of integration in comparison to an SoC. Hybrid integrated circuits are somewhat similar to SiPs, however they tend to use older or less advanced technology (tend to use single layer circuit boards or substrates, not use die stacking, do not use flip chip or BGA for connecting components or dies, use only wire bonding for connecting dies or Small outline integrated circuit packages, use Dual in-line packages, or Single in-line packages for interfacing outside the Hybrid IC instead of BGA, etc.).[9]

SiP technology is primarily being driven by early market trends in wearables, mobile devices and the internet of things which do not demand the high numbers of produced units as in the established consumer and business SoC market. As the internet of things becomes more of a reality and less of a vision, there is innovation going on at the system on a chip and SiP level so that microelectromechanical (MEMS) sensors can be integrated on a separate die and control the connectivity.[10]

SiP solutions may require multiple packaging technologies, such as flip chip, wire bonding, wafer-level packaging, Through-silicon vias (TSVs), chiplets and more.[11][12]


See also


  1. ^ INEMI System in Package Technology,, June 2005, Retrieved 2024-01-24
  2. ^ By Pushkar Apte, W. R. Bottoms, William Chen and George Scalise, IEEE Spectrum. “Advanced Chip Packaging Satisfies Smartphone Needs.” February 8, 2011. Retrieved July 31, 2015.
  3. ^ System-in-Package (SiP), a success story // AnySilicon, February 21, 2020
  4. ^ "System-in-Package (SiP), a success story". 21 February 2020.
  5. ^ "Here's why System-in-Package is a big deal for Apple's upcoming iWatch, and everything else". 30 April 2014.
  6. ^ "MCM, SiP, SoC, and Heterogeneous Integration Defined and Explained". 7 August 2017.
  7. ^ "SiP is the new SoC @ 56thDAC". 21 February 2024.
  8. ^ By R. Wayne Johnson, Mark Strickland and David Gerke, NASA Electronic Parts and Packaging Program. “3-D Packaging: A Technology Review.” June 23, 2005. Retrieved July 31, 2015.
  9. ^ Ko, Cheng-Ta; Yang, Henry; Lau, John; Li, Ming; Li, Margie; Lin, Curry; Lin, J. W.; Chang, Chieh-Lin; Pan, Jhih-Yuan; Wu, Hsing-Hui; Chen, Yu-Hua; Chen, Tony; Xu, Iris; Lo, Penny; Fan, Nelson (2018-10-01). "Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration". Journal of Microelectronics and Electronic Packaging. 15 (4): 141–147. doi:10.4071/imaps.734552. ISSN 1551-4897. S2CID 226940879.
  10. ^ By Ed Sperling, Semiconductor Engineering. “Why Packaging Matters.” November 19, 2015. Retrieved March 16, 2016.
  11. ^ By Tech Search International and Chip Scale Review Staff, Chip Scale Review. “Major OSATs positioned for growth opportunities in SiP.” May/June Issue. Retrieved June 22, 2016.
  12. ^ "SiP is the new SoC @ 56thDAC". 21 February 2024.