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An Altera MAX 7000-series CPLD with 2500 gates.
An Altera MAX 7000-series CPLD with 2500 gates.
Die of an Altera EPM7032 EEPROM-based Complex Programmable Logic Device (CPLD). Die size 3446x2252 µm. Technology node 1 µm.
Die of an Altera EPM7032 EEPROM-based Complex Programmable Logic Device (CPLD). Die size 3446x2252 µm. Technology node 1 µm.

A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The main building block of the CPLD is a macrocell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.

Features

Some of the CPLD features are in common with PALs:

Other features are in common with FPGAs:

The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD, which allows CPLDs to be used for "boot loader" functions, before handing over control to other devices not having their own permanent program storage. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.[1]

Distinctions

CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs. These in turn were preceded by standard logic products, that offered no programmability and were used to build logic functions by physically wiring several standard logic chips (or hundreds of them) together (usually with wiring on a printed circuit board or boards, but sometimes, especially for prototyping, using wire wrap wiring).

The main distinction between FPGA and CPLD device architectures is that CPLDs are internally based on look-up tables (LUTs) while FPGAs use logic blocks.

See also

References

  1. ^ "Complex Programmable Logic Device". blogspot.com. May 2008. Retrieved 2013-11-17.