ARM Cortex-M0 and Cortex-M3 microcontroller ICs from NXP and Silicon Labs (Energy Micro)
ARM Cortex-M0 and Cortex-M3 microcontroller ICs from NXP and Silicon Labs (Energy Micro)
Die from a STM32F100C4T6B IC.24 MHz ARM Cortex-M3 microcontroller with 16 KB flash memory, 4 KB RAM. Manufactured by STMicroelectronics.
Die from a STM32F100C4T6B IC.
24 MHz ARM Cortex-M3 microcontroller with 16 KB flash memory, 4 KB RAM. Manufactured by STMicroelectronics.

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by Arm Holdings. These cores are optimized for low-cost and energy-efficient integrated circuits, which have been embedded in tens of billions of consumer devices.[1] Though they are most often the main component of microcontroller chips, sometimes they are embedded inside other types of chips too. The Cortex-M family consists of Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M23, Cortex-M33, Cortex-M35P, Cortex-M55.[2][3][4][5][6][7][8] The Cortex-M4 / M7 / M33 / M35P / M55 cores have an FPU silicon option, and when included in the silicon these cores are sometimes known as "Cortex-Mx with FPU" or "Cortex-MxF", where 'x' is the core variant.

Overview

32-bit
Year Core
2004 Cortex-M3
2007 Cortex-M1
2009 Cortex-M0
2010 Cortex-M4
2012 Cortex-M0+
2014 Cortex-M7
2016 Cortex-M23
2016 Cortex-M33
2018 Cortex-M35P
2020 Cortex-M55
2022 Cortex-M85

See also: ARM architecture and List of ARM cores

The ARM Cortex-M family are ARM microprocessor cores which are designed for use in microcontrollers, ASICs, ASSPs, FPGAs, and SoCs. Cortex-M cores are commonly used as dedicated microcontroller chips, but also are "hidden" inside of SoC chips as power management controllers, I/O controllers, system controllers, touch screen controllers, smart battery controllers, and sensors controllers.

The main difference from the Cortex-A core is that there is no memory management unit (MMU). A full-fledged operating system does not normally run on this class of processor.

Though 8-bit microcontrollers were very popular in the past, Cortex-M has slowly been chipping away at the 8-bit market as the prices of low-end Cortex-M chips have moved downward. Cortex-M have become a popular replacements for 8-bit chips in applications that benefit from 32-bit math operations, and replacing older legacy ARM cores such as ARM7 and ARM9.

License

Arm Holdings neither manufactures nor sells CPU devices based on its own designs, but rather licenses the processor architecture to interested parties. Arm offers a variety of licensing terms, varying in cost and deliverables. To all licensees, Arm provides an integratable hardware description of the ARM core, as well as complete software development toolset and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated Device Manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions (including floating point), optimizations for size, debug support, etc. To determine which components have been included in a particular ARM CPU chip, consult the manufacturer datasheet and related documentation.

Some of the silicon options for the Cortex-M cores are:

ARM Cortex-M optional components
ARM Core Cortex
M0[2]
Cortex
M0+[3]
Cortex
M1[4]
Cortex
M3[5]
Cortex
M4[6]
Cortex
M7[7]
Cortex
M23[8]
Cortex
M33[12]
Cortex
M35P
SysTick 24-bit Timer Optional
(0,1)
Optional
(0,1)
Optional
(0,1)
Yes
(1)
Yes
(1)
Yes
(1)
Optional
(0,1,2)
Yes
(1,2)
Yes
(1,2)
Single-cycle I/O port No Optional No No No No Optional No No
Bit-Band memory No[13] No[13] No* Optional Optional Optional No No No
Memory Protection
Unit (MPU)
No Optional
(0,8)
No Optional
(0,8)
Optional
(0,8)
Optional
(0,8,16)
Optional
(0,4,8,12,16)
Optional
(0,4,8,12,16)
Optional
*
Security Attribution
Unit (SAU) and
Stack Limits
No No No No No No Optional
(0,4,8)
Optional
(0,4,8)
Optional
*
Instruction TCM No No Optional No No Optional No No No
Data TCM No No Optional No No Optional No No No
Instruction Cache No[14] No[14] No[14] No[14] No[14] Optional No No Optional
Data Cache No[14] No[14] No[14] No[14] No[14] Optional No No No
Vector Table Offset
Register (VTOR)
No Optional
(0,1)
Optional
(0,1)
Optional
(0,1)
Optional
(0,1)
Optional
(0,1)
Optional
(0,1,2)
Yes
(1,2)
Yes
(1,2)

Additional silicon options:[9][10]

Instruction sets

See also: ARM architecture § Instruction set

The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture,[9] the Cortex-M3 implements the ARMv7-M architecture,[10] the Cortex-M4 / Cortex-M7 implements the ARMv7E-M architecture,[10] the Cortex-M23 / M33 / M35P implement the ARMv8-M architecture,[15] and the Cortex-M55 implements the ARMv8.1-M architecture.[15] The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / Cortex-M0+ / Cortex-M1 can execute without modification on the Cortex-M3 / Cortex-M4 / Cortex-M7. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4 / Cortex-M7 / Cortex-M33 / Cortex-M35P.[9][10] Only Thumb-1 and Thumb-2 instruction sets are supported in Cortex-M architectures; the legacy 32-bit ARM instruction set isn't supported.

All Cortex-M cores implement a common subset of instructions that consists of most Thumb-1, some Thumb-2, including a 32-bit result multiply. The Cortex-M0 / Cortex-M0+ / Cortex-M1 / Cortex-M23 were designed to create the smallest silicon die, thus having the fewest instructions of the Cortex-M family.

The Cortex-M0 / M0+ / M1 include Thumb-1 instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).[9] The Cortex-M3 / M4 / M7 / M33 / M35P have all base Thumb-1 and Thumb-2 instructions. The Cortex-M3 adds three Thumb-1 instructions, all Thumb-2 instructions, hardware integer divide, and saturation arithmetic instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit (VFPv4-SP). The Cortex-M7 adds an optional double-precision FPU (VFPv5).[7][10] The Cortex-M23 / M33 add TrustZone instructions.

ARM Cortex-M instruction variations
Arm Core Cortex
M0[2]
Cortex
M0+[3]
Cortex
M1[4]
Cortex
M3[5]
Cortex
M4[6]
Cortex
M7[7]
Cortex
M23[8]
Cortex
M33[12]
Cortex
M35P
Cortex
M55
ARM architecture ARMv6-M[9] ARMv6-M[9] ARMv6-M[9] ARMv7-M[10] ARMv7E-M[10] ARMv7E-M[10] ARMv8-M
Baseline[15]
ARMv8-M
Mainline[15]
ARMv8-M
Mainline[15]
Armv8.1-M
Computer architecture Von Neumann Von Neumann Von Neumann Harvard Harvard Harvard Von Neumann Harvard Harvard Harvard
Instruction pipeline 3 stages 2 stages 3 stages 3 stages 3 stages 6 stages 2 stages 3 stages 3 stages 4 to 5 stages
Thumb-1 instructions Most Most Most Entire Entire Entire Most Entire Entire Entire
Thumb-2 instructions Some Some Some Entire Entire Entire Some Entire Entire Entire
Multiply instructions
32x32 = 32-bit result
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Multiply instructions
32x32 = 64-bit result
No No No Yes Yes Yes No Yes Yes Yes
Divide instructions
32/32 = 32-bit quotient
No No No Yes Yes Yes Yes Yes Yes Yes
Saturated instructions No No No Some Yes Yes No Yes Yes Yes
DSP instructions No No No No Yes Yes No Optional Optional Optional
Single-Precision (SP)
Floating-point instructions
No No No No Optional Optional No Optional Optional Optional
Double-Precision (DP)
Floating-point instructions
No No No No No Optional No No No Optional
Half-Precisions (HP) No No No No No No No No No Optional
TrustZone instructions No No No No No No Optional Optional Optional Optional
Co-processor instructions No No No No No No No Optional Optional Optional
Helium technology No No No No No No No No No Optional
Interrupt latency
(if zero-wait state RAM)
16 cycles 15 cycles 23 for NMI
26 for IRQ
12 cycles 12 cycles 12 cycles
14 worst case
15 no security ext
27 security ext
12 no security ext
?? security ext
TBD TBD
ARM Cortex-M instruction groups
Group Instr
bits
Instructions Cortex
M0,M0+,M1
Cortex
M3
Cortex
M4
Cortex
M7
Cortex
M23
Cortex
M33,M35P
Cortex
M55
Thumb-1 16 ADC, ADD, ADR, AND, ASR, B, BIC, BKPT, BLX, BX, CMN, CMP, CPS, EOR, LDM, LDR, LDRB, LDRH, LDRSB, LDRSH, LSL, LSR, MOV, MUL, MVN, NOP, ORR, POP, PUSH, REV, REV16, REVSH, ROR, RSB, SBC, SEV, STM, STR, STRB, STRH, SUB, SVC, SXTB, SXTH, TST, UXTB, UXTH, WFE, WFI, YIELD Yes Yes Yes Yes Yes Yes Yes
Thumb-1 16 CBNZ, CBZ No Yes Yes Yes Yes Yes Yes
Thumb-1 16 IT No Yes Yes Yes No Yes Yes
Thumb-2 32 BL, DMB, DSB, ISB, MRS, MSR Yes Yes Yes Yes Yes Yes Yes
Thumb-2 32 SDIV, UDIV, MOVT, MOVW No Yes Yes Yes Yes Yes Yes
Thumb-2 32 ADC, ADD, ADR, AND, ASR, B, BFC, BFI, BIC, CDP, CLREX, CLZ, CMN, CMP, DBG, EOR, LDC, LDM, LDR, LDRB, LDRBT, LDRD, LDREX, LDREXB, LDREXH, LDRH, LDRHT, LDRSB, LDRSBT, LDRSH, LDRSHT, LDRT, LSL, LSR, MCR, MCRR, MLA, MLS, MRC, MRRC, MUL, MVN, NOP, ORN, ORR, PLD, PLDW, PLI, POP, PUSH, RBIT, REV, REV16, REVSH, ROR, RRX, RSB, SBC, SBFX, SEV, SMLAL, SMULL, SSAT, STC, STM, STR, STRB, STRBT, STRD, STREX, STREXB, STREXH, STRH, STRHT, STRT, SUB, SXTB, SXTH, TBB, TBH, TEQ, TST, UBFX, UMLAL, UMULL, USAT, UXTB, UXTH, WFE, WFI, YIELD No Yes Yes Yes No Yes Yes
DSP 32 PKH, QADD, QADD16, QADD8, QASX, QDADD, QDSUB, QSAX, QSUB, QSUB16, QSUB8, SADD16, SADD8, SASX, SEL, SHADD16, SHADD8, SHASX, SHSAX, SHSUB16, SHSUB8, SMLABB, SMLABT, SMLATB, SMLATT, SMLAD, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, SMLAWB, SMLAWT, SMLSD, SMLSLD, SMMLA, SMMLS, SMMUL, SMUAD, SMULBB, SMULBT, SMULTT, SMULTB, SMULWT, SMULWB, SMUSD, SSAT16, SSAX, SSUB16, SSUB8, SXTAB, SXTAB16, SXTAH, SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSAX, UHSUB16, UHSUB8, UMAAL, UQADD16, UQADD8, UQASX, UQSAX, UQSUB16, UQSUB8, USAD8, USADA8, USAT16, USAX, USUB16, USUB8, UXTAB, UXTAB16, UXTAH, UXTB16 No No Yes Yes No Optional Yes
SP Float 32 VABS, VADD, VCMP, VCMPE, VCVT, VCVTR, VDIV, VLDM, VLDR, VMLA, VMLS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP, VPUSH, VSQRT, VSTM, VSTR, VSUB No No Optional Optional No Optional Optional
DP Float 32 VCVTA, VCVTM, VCVTN, VCVTP, VMAXNM, VMINNM, VRINTA, VRINTM, VRINTN, VRINTP, VRINTR, VRINTX, VRINTZ, VSEL No No No Optional No No Optional
TrustZone 16 BLXNS, BXNS No No No No Optional Optional Optional
TrustZone 32 SG, TT, TTT, TTA, TTAT No No No No Optional Optional Optional
Co-processor 16 CDP, CDP2, MCR, MCR2, MCRR, MCRR2, MRC, MRC2, MRRC, MRRC2 No No No No No Optional Optional

Deprecations

The ARM architecture for ARM Cortex-M series removed some features from older legacy cores:[9][10]

The capabilities of the 32-bit ARM instruction set is duplicated in many ways by the Thumb-1 and Thumb-2 instruction sets, but some ARM features don't have a similar feature:

The 16-bit Thumb-1 instruction set has evolved over time since it was first released in the legacy ARM7T cores with the ARMv4T architecture. New Thumb-1 instructions were added as each legacy ARMv5 / ARMv6 / ARMv6T2 architectures were released. Some 16-bit Thumb-1 instructions were removed from the Cortex-M cores:

Cortex-M0

Cortex-M0
Architecture and classification
MicroarchitectureARMv6-M
Instruction setThumb-1 (most),
Thumb-2 (some)

The Cortex-M0 core is optimized for small silicon die size and use in the lowest price chips.

Key features of the Cortex-M0 core are:[2]

Silicon options:

Chips

nRF51822
nRF51822

The following microcontrollers are based on the Cortex-M0 core:

The following chips have a Cortex-M0 as a secondary core:

Cortex-M0+

Cortex-M0+
Architecture and classification
MicroarchitectureARMv6-M
Instruction setThumb-1 (most),
Thumb-2 (some)
NXP (Freescale) FRDM-KL25Z Board with KL25Z128VLK (Kinetis L)
NXP (Freescale) FRDM-KL25Z Board with KL25Z128VLK (Kinetis L)

The Cortex-M0+ is an optimized superset of the Cortex-M0. The Cortex-M0+ has complete instruction set compatibility with the Cortex-M0 thus allowing the use of the same compiler and debug tools. The Cortex-M0+ pipeline was reduced from 3 to 2 stages, which lowers the power usage. In addition to debug features in the existing Cortex-M0, a silicon option can be added to the Cortex-M0+ called the Micro Trace Buffer (MTB) which provides a simple instruction trace buffer. The Cortex-M0+ also received Cortex-M3 and Cortex-M4 features, which can be added as silicon options, such as the memory protection unit (MPU) and the vector table relocation.[3]

Key features of the Cortex-M0+ core are:[3]

Silicon options:

Chips

The following microcontrollers are based on the Cortex-M0+ core:

The following chips have a Cortex-M0+ as a secondary core:

The smallest ARM microcontrollers are of the Cortex-M0+ type (as of 2014, smallest at 1.6 mm by 2 mm in a chip-scale package is Kinetis KL03).[16]

On 21 June 2018, the "world's smallest computer'", or computer device was announced – based on the ARM Cortex-M0+ (and including RAM and wireless transmitters and receivers based on photovoltaics) – by University of Michigan researchers at the 2018 Symposia on VLSI Technology and Circuits with the paper "A 0.04mm3 16nW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement." The device is 1/10th the size of IBM's previously claimed world-record-sized computer from months back in March 2018, which is smaller than a grain of salt.

Cortex-M1

Cortex-M1
Architecture and classification
MicroarchitectureARMv6-M
Instruction setThumb-1 (most),
Thumb-2 (some)

The Cortex-M1 is an optimized core especially designed to be loaded into FPGA chips.

Key features of the Cortex-M1 core are:[4]

Silicon options:

Chips

The following vendors support the Cortex-M1 as soft-cores on their FPGA chips:

Cortex-M3

Cortex-M3
Architecture and classification
MicroarchitectureARMv7-M
Instruction setThumb-1, Thumb-2,
Saturated (some), Divide
Arduino Due board with Atmel ATSAM3X8E (ARM Cortex-M3 core) microcontroller
Arduino Due board with Atmel ATSAM3X8E (ARM Cortex-M3 core) microcontroller
NXP LPCXpresso Development Board with LPC1343
NXP LPCXpresso Development Board with LPC1343

Key features of the Cortex-M3 core are:[5][19]

Silicon options:

Chips

The following microcontrollers are based on the Cortex-M3 core:

The following chips have a Cortex-M3 as a secondary core:

The following FPGAs include a Cortex-M3 core:

The following vendors support the Cortex-M3 as soft-cores on their FPGA chips:

Cortex-M4

Cortex-M4
Architecture and classification
MicroarchitectureARMv7E-M
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
Divide, FPU (SP)
Silicon Labs (Energy Micro) Wonder Gecko STK Board with EFM32WG990
Silicon Labs (Energy Micro) Wonder Gecko STK Board with EFM32WG990
TI Stellaris Launchpad Board with LM4F120
TI Stellaris Launchpad Board with LM4F120

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP instructions, and optional floating-point unit (FPU). A core with an FPU is known as Cortex-M4F.

Key features of the Cortex-M4 core are:[6]

Silicon options:

Chips

nRF52833 on a micro bit v2
nRF52833 on a micro bit v2
STM32F407IGH6
STM32F407IGH6

The following microcontrollers are based on the Cortex-M4 core:

The following microcontrollers are based on the Cortex-M4F (M4 + FPU) core:

The following chips have either a Cortex-M4 or M4F as a secondary core:

Cortex-M7

Cortex-M7
Architecture and classification
MicroarchitectureARMv7E-M
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
Divide, FPU (SP & DP)

The Cortex-M7 is a high-performance core with almost double the power efficiency of the older Cortex-M4. It features a 6-stage superscalar pipeline with branch prediction and an optional floating-point unit capable of single-precision and optionally double-precision operations.[22][23] The instruction and data buses have been enlarged to 64-bit wide over the previous 32-bit buses. If a core contains an FPU, it is known as a Cortex-M7F, otherwise it is a Cortex-M7.

Key features of the Cortex-M7 core are:[7]

Silicon options:

Chips

The following microcontrollers are based on the Cortex-M7 core:

Cortex-M23

Cortex-M23
Architecture and classification
MicroarchitectureARMv8-M Baseline
Instruction setThumb-1 (most),
Thumb-2 (some),
Divide, TrustZone

The Cortex-M23 core was announced in October 2016[24] and based on the newer ARMv8-M architecture that was previously announced in November 2015.[25] Conceptually the Cortex-M23 is similar to a Cortex-M0+ plus integer divide instructions and TrustZone security features, and also has a 2-stage instruction pipeline.

Key features of the Cortex-M23 core are:[8][24]

Silicon options:

Chips

The following microcontrollers are based on the Cortex-M23 core:

Cortex-M33

Cortex-M33
Architecture and classification
MicroarchitectureARMv8-M Mainline
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
Divide, FPU (SP),
TrustZone, Co-processor

The Cortex-M33 core was announced in October 2016[24] and based on the newer ARMv8-M architecture that was previously announced in November 2015.[25] Conceptually the Cortex-M33 is similar to a cross of Cortex-M4 and Cortex-M23, and also has a 3-stage instruction pipeline.

Key features of the Cortex-M33 core are:[12][24]

Silicon options:

Chips

The following microcontrollers are based on the Cortex-M33 core:

Cortex-M35P

Cortex-M35P
Architecture and classification
MicroarchitectureARMv8-M Mainline
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
Divide, FPU (SP),
TrustZone, Co-processor

The Cortex-M35P core was announced in May 2018. It is conceptually a Cortex-M33 core with a new instruction cache, plus new tamper-resistant hardware concepts borrowed from the ARM SecurCore family, and configurable parity and ECC features.[26]

Limited public information is currently available for the Cortex-M35P until its Technical Reference Manual is released.

Chips

The following microcontrollers are based on the Cortex-M35P core:

Cortex-M55

Cortex-M55
Architecture and classification
MicroarchitectureARMv8.1-M Mainline Helium
Instruction setThumb-1, Thumb-2,
Saturated, DSP,
Divide, FPU (VFPv5),
TrustZone, Coprocessor, MVE

The Cortex-M55 core was announced in February 2020 and is based on the Armv8.1-M architecture that was previously announced in February 2019. It also has a 4-stage instruction pipeline.

Key features of the Cortex-M55 core include:

Silicon options:

Chips

Development tools

Segger J-Link PRO. Debug probe with SWD or JTAG interface to target ARM chip, and USB or Ethernet interfaces to host computer.
Segger J-Link PRO. Debug probe with SWD or JTAG interface to target ARM chip, and USB or Ethernet interfaces to host computer.

Main article: List of ARM Cortex-M development tools

Documentation

The documentation for ARM chips is extensive. In the past, 8-bit microcontroller documentation would typically fit in a single document, but as microcontrollers have evolved, so has everything required to support them. A documentation package for ARM chips typically consists of a collection of documents from the IC manufacturer as well as the CPU core vendor (Arm Holdings).

A typical top-down documentation tree is:

Documentation tree (top to bottom)
  1. IC manufacturer website.
  2. IC manufacturer marketing slides.
  3. IC manufacturer datasheet for the exact physical chip.
  4. IC manufacturer reference manual that describes common peripherals and aspects of a physical chip family.
  5. ARM core website.
  6. ARM core generic user guide.
  7. ARM core technical reference manual.
  8. ARM architecture reference manual.

IC manufacturers have additional documents, such as: evaluation board user manuals, application notes, getting started guides, software library documents, errata, and more. See External links section for links to official Arm documents.

See also

References

  1. ^ ARM Cortex-M website; arm.com
  2. ^ a b c d Cortex-M0 Technical Reference Manual Revision r0p0; Arm Holdings.
  3. ^ a b c d e Cortex-M0+ Technical Reference Manual Revision r0p1; Arm Holdings.
  4. ^ a b c d Cortex-M1 r1p0 Technical Reference Manual; Arm Holdings.
  5. ^ a b c d Cortex-M3 r2p1 Technical Reference Manual; Arm Holdings.
  6. ^ a b c d Cortex-M4 Technical Reference Manual Revision r0p1; Arm Holdings.
  7. ^ a b c d e Cortex-M7 Technical Reference Manual; Arm Holdings.
  8. ^ a b c d Cortex-M23 r1p0 Technical Reference Manual; Arm Holdings.
  9. ^ a b c d e f g h i j k l m n o p q r "ARMv6-M Architecture Reference Manual". Arm Holdings. 29 June 2018. Archived from the original on 22 January 2021.
  10. ^ a b c d e f g h i j k l m n o p q r "ARMv7-M Architecture Reference Manual". Arm Holdings. 15 February 2021.
  11. ^ a b c d Cortex-M3 Embedded Software Development; App Note 179; Arm Holdings.
  12. ^ a b c Cortex-M33 r0p3 Technical Reference Manual; Arm Holdings.
  13. ^ a b c Cortex-M System Design Kit; Arm Holdings.
  14. ^ a b c d e f g h i j ARM Cortex-M Programming Guide to Memory Barrier Instructions; Section 3.6 System implementation requirements; AppNote 321; arm.com
  15. ^ a b c d e f g h ARMv8-M Architecture Reference Manual; Arm Holdings.
  16. ^ Fingas, Jon (25 February 2014). "Freescale makes the world's smallest ARM controller chip even tinier". Retrieved 2 October 2014.
  17. ^ GOWIN Semiconductor joins ARM DesignStart offering free ARM Cortex-M1 Processors for its FPGA product families
  18. ^ Cortex-M1 DesignStart FPGA XilinxEdition
  19. ^ Sadasivan, Shyam. "An Introduction to the ARM Cortex-M3 Processor" (PDF). Arm Holdings. Archived from the original (PDF) on July 26, 2014.
  20. ^ "The Samsung Exynos 7420 Deep Dive - Inside a Modern 14nm SoC". AnandTech. Retrieved 2015-06-15.
  21. ^ Cortex-M3 DesignStart FPGA XilinxEdition
  22. ^ "Cortex-M7 Processor". Arm Holdings. Retrieved 2014-09-24.
  23. ^ "ARM Supercharges MCU Market with High Performance Cortex-M7 Processor". arm.com (Press release). September 24, 2014.
  24. ^ a b c d New ARM Cortex-M processors offer the next industry standard for secure IoT; Arm Holdings; October 25, 2016.
  25. ^ a b ARMv8-M Architecture Simplifies Security for Smart Embedded Devices; Arm Holdings; November 10, 2015.
  26. ^ "Cortex-M35P Processor". Arm Holdings. Retrieved 2018-06-04.

Further reading

ARM Cortex-M official documents
ARM
core
Bit
width
ARM
website
ARM generic
user guide
ARM technical
reference manual
ARM architecture
reference manual
Cortex-M0 32 Link Link Link ARMv6-M
Cortex-M0+ 32 Link Link Link ARMv6-M
Cortex-M1 32 Link Link Link ARMv6-M
Cortex-M3 32 Link Link Link ARMv7-M
Cortex-M4 32 Link Link Link ARMv7E-M
Cortex-M7 32 Link Link Link ARMv7E-M
Cortex-M23 32 Link Link Link ARMv8-M
Cortex-M33 32 Link Link Link ARMv8-M
Cortex-M35P 32 Link TBD TBD ARMv8-M
Cortex-M55 32 Link TBD TBD ARMv8.1-M
Quick reference cards
Migrating
Other