|Max. CPU clock rate||1 MHz to 3 MHz|
|Architecture and classification|
|Instruction set||MOS 6502|
The MOS Technology 6502 (typically pronounced "sixty-five-oh-two" or "six-five-oh-two") is an 8-bit microprocessor that was designed by a small team led by Chuck Peddle for MOS Technology. The design team had formerly worked at Motorola on the Motorola 6800 project; the 6502 is essentially a simplified, less expensive and faster version of that design.
When it was introduced in 1975, the 6502 was the least expensive microprocessor on the market by a considerable margin. It initially sold for less than one-sixth the cost of competing designs from larger companies, such as the 6800 or Intel 8080. Its introduction caused rapid decreases in pricing across the entire processor market. Along with the Zilog Z80, it sparked a series of projects that resulted in the home computer revolution of the early 1980s.
Popular video game consoles and computers, such as the Atari 2600, Atari 8-bit family, Apple II, Nintendo Entertainment System, Commodore 64, Atari Lynx, BBC Micro and others, use the 6502 or variations of the basic design. Soon after the 6502's introduction, MOS Technology was purchased outright by Commodore International, who continued to sell the microprocessor and licenses to other manufacturers. In the early days of the 6502, it was second-sourced by Rockwell and Synertek, and later licensed to other companies.
In 1981, the Western Design Center started development of a CMOS version, the 65C02. This continues to be widely used in embedded systems, with estimated production volumes in the hundreds of millions.
The 6502 was designed by many of the same engineers that had designed the Motorola 6800 microprocessor family. Motorola started the 6800 microprocessor project in 1971 with Tom Bennett as the main architect. The chip layout began in late 1972, the first 6800 chips were fabricated in February 1974 and the full family was officially released in November 1974. John Buchanan was the designer of the 6800 chip and Rod Orgill, who later did the 6501, assisted Buchanan with circuit analyses and chip layout. Bill Mensch joined Motorola in June 1971 after graduating from the University of Arizona (at age 26). His first assignment was helping define the peripheral ICs for the 6800 family and later he was the principal designer of the 6820 Peripheral Interface Adapter (PIA). Motorola's engineers could run analog and digital simulations on an IBM 370-165 mainframe computer. Bennett hired Chuck Peddle in 1973 to do architectural support work on the 6800 family products already in progress. He contributed in many areas, including the design of the 6850 ACIA (serial interface).
Motorola's target customers were established electronics companies such as Hewlett-Packard, Tektronix, TRW, and Chrysler. In May 1972, Motorola's engineers began visiting select customers and sharing the details of their proposed 8-bit microprocessor system with ROM, RAM, parallel and serial interfaces. In early 1974, they provided engineering samples of the chips so that customers could prototype their designs. Motorola's "total product family" strategy did not focus on the price of the microprocessor, but on reducing the customer's total design cost. They offered development software on a timeshare computer, the "EXORciser" debugging system, onsite training and field application engineer support. Both Intel and Motorola had initially announced a $360 price for a single microprocessor. The actual price for production quantities was much less. Motorola offered a design kit containing the 6800 with six support chips for $300.
Peddle, who would accompany the salespeople on customer visits, found that customers were put off by the high cost of the microprocessor chips. At the same time, these visits invariably resulted in the engineers he presented to producing lists of required instructions that were much smaller than "all these fancy instructions" that had been included in the 6800. Peddle and other team members started outlining the design of an improved feature, reduced size microprocessor. At that time, Motorola's new semiconductor fabrication facility in Austin, Texas, was having difficulty producing MOS chips, and mid-1974 was the beginning of a year-long recession in the semiconductor industry. Also, many of the Mesa, Arizona employees were displeased with the upcoming relocation to Austin, Texas.
Motorola's Semiconductor Products Division management was overwhelmed with problems and showed no interest in Peddle's low-cost microprocessor proposal. Eventually Peddle was given an official letter telling him to stop working on the system. Peddle responded to the order by informing Motorola that the letter represented an official declaration of "project abandonment", and as such, the intellectual property he had developed to that point was now his. In a November 1975 interview, Motorola's Chairman, Robert Galvin, ultimately agreed that Peddle's concept was a good one and that the division missed an opportunity, "We did not choose the right leaders in the Semiconductor Products division." The division was reorganized and the management replaced. The new group vice-president John Welty said, "The semiconductor sales organization lost its sensitivity to customer needs and couldn't make speedy decisions."
Peddle began looking outside Motorola for a source of funding for this new project. He initially approached Mostek CEO L. J. Sevin, but he declined. Sevin later admitted this was because he was afraid Motorola would sue them.
While Peddle was visiting Ford Motor Company on one of his sales trips, Bob Johnson, later head of Ford's engine automation division, mentioned that their former colleague John Paivinen had moved to General Instrument and taught himself semiconductor design. Paivinen then formed MOS Technology in Valley Forge, Pennsylvania in 1969 with two other executives from General Instrument, Mort Jaffe and Don McLaughlin. Allen-Bradley, a supplier of electronic components and industrial controls, acquired a majority interest in 1970. The company designed and fabricated custom ICs for customers and had developed a line of calculator chips.
After the Mostek efforts fell through, Peddle approached Paivinen, who "immediately got it". On 19 August 1974, Chuck Peddle, Bill Mensch, Rod Orgill, Harry Bawcom, Ray Hirt, Terry Holdt, and Wil Mathys left Motorola to join MOS. Mike Janes joined later. Of the seventeen chip designers and layout people on the 6800 team, eight left. The goal of the team was to design and produce a low-cost microprocessor for embedded applications and to target as wide as possible a customer base. This would be possible only if the microprocessor was low cost, and the team set the price goal at $5 in volume. Mensch later stated the goal was not the processor price itself, but to create a set of chips that could sell at $20 to compete with the recently-introduced Intel 4040 that sold for $29 in a similar complete chipset.
Chips are produced by printing multiple copies of the chip design on the surface of a "wafer", a thin disk of highly pure silicon. Smaller chips can be printed in greater numbers on the same wafer, decreasing their relative price. Additionally, wafers always include some number of tiny physical defects that are scattered across the surface. Any chip printed in that location will fail and has to be discarded. Smaller chips mean any single copy is less likely to be printed on a defect. For both of these reasons, the cost of the final product is strongly dependent on the size of the chip design.
The original 6800 chips were intended to be 180 mils × 180 mils[a] (4.6 mm × 4.6 mm), but layout was completed at 212 mils × 212 mils (5.4 mm × 5.4 mm), or an area of 29.0 mm2. For the new design, the cost goal demanded a size goal of 153 mils × 168 mils (3.9 mm × 4.3 mm), or an area of 16.6 mm2. Several new techniques would be needed to hit this goal.
There were two significant advances that arrived in the market just as the 6502 was being designed that provided significant cost reductions. The first was the move to depletion-load NMOS. The 6800 used an early NMOS process that required three supply voltages, but one of the chip's features was an onboard voltage doubler that allowed a single +5 V supply be used for +5, −5 and +12 V internally, as opposed to other chips of the era like the Intel 8080 that required three separate supply pins. While this feature reduced the complexity of the power supply and pin layout, it still required separate power rails to the various gates on the chip, driving up complexity and size. By moving to the new depletion-load design, a single +5 V supply was all that was needed, eliminating all of this complexity.
A further practical advantage was that the clock signal for earlier CPUs had to be strong enough to survive all the dissipation as it traveled through the circuits, which almost always required a separate external chip that could supply a powerful signal. With the reduced power requirements of NMOS, the clock could be moved onto the chip, simplifying the overall computer design. These changes greatly reduced complexity and the cost of implementing a complete system.
Another change that was taking place was the introduction of projection masking. Previously, chips were patterned onto the surface of the wafer by placing a mask on the surface of the wafer and then shining a bright light on it. The masks often picked up tiny bits of dirt or photoresist as they were lifted off the chip, causing flaws in those locations on any subsequent masking. With complex designs like CPUs, 5 or 6 such masking steps would be used, and the chance that at least one of these steps would introduce a flaw was very high. In most cases, 90% of such designs were flawed, resulting in a 10% yield. The price of the working examples had to cover the production cost of the 90% that were thrown away.
In 1973, Perkin-Elmer introduced the Micralign system, which projected an image of the mask on the wafer instead of requiring direct contact. Masks no longer picked up dirt from the wafers and lasted on the order of 100,000 uses rather than 10. This eliminated step-to-step failures and the high flaw rates formerly seen on complex designs. Yields on CPUs immediately jumped from 10% to 60 or 70%. This meant the price of the CPU declined roughly the same amount and the microprocessor suddenly became a commodity device.
MOS Technology's existing fabrication lines were based on the older PMOS technology, they had not yet begun to work with NMOS when the team arrived. Paivinen promised to have an NMOS line up and running in time to begin the production of the new CPU. He delivered on the promise, the new line was ready by June 1975.
Chuck Peddle, Rod Orgill, and Wil Mathys designed the initial architecture of the new processors. A September 1975 article in EDN magazine gives this summary of the design:
The MOS Technology 650X family represents a conscious attempt of eight former Motorola employees who worked on the development of the 6800 system to put out a part that would replace and outperform the 6800, yet undersell it. With the benefit of hindsight gained on the 6800 project, the MOS Technology team headed by Chuck Peddle, made the following architectural changes in the Motorola CPU…
The main change in terms of chip size was the elimination of the tri-state drivers from the address bus outputs. This had been included in the 6800 to allow it to work with other chips in direct memory access (DMA) and co-processing roles, at the cost of significant die space. In practice, using such a system required the other devices to be similarly complex, and designers instead tended to use off-chip systems to coordinate such access. The 6502 simply removed this feature, in keeping with its design as an inexpensive controller being used for specific tasks and communicating with simple devices. Peddle suggested that anyone that actually required this style of access could implement it with a single 74158.[b]
The next major difference was to simplify the registers. To start with, one of the two accumulators was removed. General-purpose registers like accumulators have to be accessed by many parts of the instruction decoder, and thus require significant amounts of wiring to move data to and from their storage. Two accumulators makes many coding tasks easier, but costs the chip design itself significant complexity. Further savings were made by reducing the stack register from 16 to 8 bits, meaning that the stack could only be 256 bytes long, which was enough for its intended role as a microcontroller.
The 16-bit IX index register was split in two, becoming X and Y. More importantly, the style of access changed; in the 6800, IX held a 16-bit address, which was offset by an 8-bit number supplied with the instruction, the two were added to produce the final address. In the 6502 (and most other designs), the 16-bit base address was stored in the instruction, and the X or Y was added to it.
Finally, the instruction set was simplified, freeing up room in the decoder and control logic. Of the original 72 instructions in the 6800, 56 were left. Among those removed were any instruction that moved data between the 6800's two accumulators, as well as a number of branch instructions inspired by the PDP-11, like the ability to directly compare two numeric values. The 6502 used a simpler system that handled comparisons by performing math on the accumulator and then examining result flags.
The chip's high-level design had to be turned into drawings of transistors and interconnects. At MOS Technology, the "layout" was a very manual process done with color pencils and vellum paper. The layout consisted of thousands of polygon shapes on six different drawings; one for each layer of the fabrication process. Given the size limits, the entire chip design had to be constantly considered. Mensch and Paivinen worked on the instruction decoder while Mensch, Peddle and Orgill worked on the ALU and registers. A further advance, developed at a party, was a way to share some of the internal wiring to allow the ALU to be reduced in size.
In spite of their best efforts, the final design ended up being 5 mils too wide. The first 6502 chips were 168 × 183 mils (4.3 × 4.7 mm), or an area of 19.8 mm2. The rotate right instruction (ROR) did not work in the first silicon, so the instruction was temporarily omitted from the published documents, but the next iteration of the design shrank the chip and corrected the rotate right instruction, which was then included in revised documentation.
MOS would introduce two microprocessors based on the same underlying design: the 6501 would plug into the same socket as the Motorola 6800, while the 6502 re-arranged the pinout to support an on-chip clock oscillator. Both would work with other support chips designed for the 6800. They would not run 6800 software because they had a different instruction set, different registers, and mostly different addressing modes. Rod Orgill was responsible for the 6501 design; he had assisted John Buchanan at Motorola on the 6800. Bill Mensch did the 6502; he was the designer of the 6820 Peripheral Interface Adapter (PIA) at Motorola. Harry Bawcom, Mike Janes and Sydney-Anne Holt helped with the layout.
MOS Technology's microprocessor introduction was different from the traditional months-long product launch. The first run of a new integrated circuit is normally used for internal testing and shared with select customers as "engineering samples". These chips often have a minor design defect or two that will be corrected before production begins. Chuck Peddle's goal was to sell the first run 6501 and 6502 chips to the attendees at the Wescon trade show in San Francisco beginning on September 16, 1975. Peddle was a very effective spokesman and the MOS Technology microprocessors were extensively covered in the trade press. One of the earliest was a full-page story on the MCS6501 and MCS6502 microprocessors in the July 24, 1975 issue of Electronics magazine. Stories also ran in EE Times (August 24, 1975), EDN (September 20, 1975), Electronic News (November 3, 1975), Byte (November 1975) and Microcomputer Digest (November 1975). Advertisements for the 6501 appeared in several publications the first week of August 1975. The 6501 would be for sale at Wescon for $20 each. In September 1975, the advertisements included both the 6501 and the 6502 microprocessors. The 6502 would cost only $25 (equivalent to $126 in 2021).
When MOS Technology arrived at Wescon, they found that exhibitors were not permitted to sell anything on the show floor. They rented the MacArthur Suite at the St. Francis Hotel and directed customers there to purchase the processors. At the suite, the processors were stored in large jars to imply that the chips were in production and readily available. The customers did not know the bottom half of each jar contained non-functional chips. The chips were $20 and $25 while the documentation package was an additional $10. Users were encouraged to make photocopies of the documents, an inexpensive way for MOS Technology to distribute product information. The preliminary data sheets listed just 55 instructions excluding the Rotate Right (ROR) instruction which did not work correctly on these early chips. The reviews in Byte and EDN noted the lack of the ROR instruction. The next revision of the layout fixed this problem and the May 1976 datasheet listed 56 instructions. Peddle wanted every interested engineer and hobbyist to have access to the chips and documentation; other semiconductor companies only wanted to deal with "serious" customers. For example, Signetics was introducing the 2650 microprocessor and its advertisements asked readers to write for information on their company letterhead.
|3||∅1 (in)||∅1 (in)||∅1 (out)|
|5||Valid memory address||Valid memory address||N.C.|
|7||Bus available||Bus available||SYNC|
|36||Data bus enable||Data bus enable||N.C.|
|37||∅2 (in)||∅2 (in)||∅0 (in)|
|38||N.C.||N.C.||Set overflow flag|
|39||Three-state control||N.C.||∅2 (out)|
The 6501/6502 introduction in print and at Wescon was an enormous success. The downside was that the extensive press coverage got Motorola's attention. In October 1975, Motorola reduced the price of a single 6800 microprocessor from $175 to $69. The $300 system design kit was reduced to $150 and it now came with a printed circuit board. On November 3, 1975, Motorola sought an injunction in Federal Court to stop MOS Technology from making and selling microprocessor products. They also filed a lawsuit claiming patent infringement and misappropriation of trade secrets. Motorola claimed that seven former employees joined MOS Technology to create that company's microprocessor products.
Motorola was a billion-dollar company with a plausible case and lawyers. On October 30, 1974, Motorola had filed numerous patent applications on the microprocessor family and was granted twenty-five patents. The first was in June 1976 and the second was to Bill Mensch on July 6, 1976, for the 6820 PIA chip layout. These patents covered the 6800 bus and how the peripheral chips interfaced with the microprocessor. Motorola began making transistors in 1950 and had a portfolio of semiconductor patents. Allen-Bradley decided not to fight this case and sold their interest in MOS Technology back to the founders. Four of the former Motorola engineers were named in the suit: Chuck Peddle, Will Mathys, Bill Mensch and Rod Orgill. All were named inventors in the 6800 patent applications. During the discovery process, Motorola found that one engineer, Mike Janes, had ignored Peddle's instructions and brought his 6800 design documents to MOS Technology. In March 1976, the now independent MOS Technology was running out of money and had to settle the case. They agreed to drop the 6501 processor, pay Motorola $200,000 and return the documents that Motorola contended were confidential. Both companies agreed to cross-license microprocessor patents. That May, Motorola dropped the price of a single 6800 microprocessor to $35. By November, Commodore had acquired MOS Technology.
With legal troubles behind them, MOS was still left with the problem of getting developers to try their processor, prompting Chuck Peddle to design the MDT-650 ("microcomputer development terminal") single-board computer. Another group inside the company designed the KIM-1, which was sold semi-complete and could be turned into a usable system with the addition of a 3rd party computer terminal and compact cassette drive. Much to their amazement, the KIM-1 sold well to hobbyists and tinkerers, as well as to the engineers to which it had been targeted. The related Rockwell AIM 65 control/training/development system also did well. The software in the AIM 65 was based on that in the MDT. Another roughly similar product was the Synertek SYM-1.
One of the first "public" uses for the design was the Apple I microcomputer, introduced in 1976. The 6502 was next used in the Commodore PET and the Apple II, both released in 1977. It was later used in the Atari 8-bit family and Acorn Atom home computers, the BBC Micro, Commodore VIC-20 and other designs both for home computers and business, such as Ohio Scientific and Oric. The 6510, a direct successor of the 6502 with a digital I/O port and a tri-state address bus, was the CPU utilized in the best-selling Commodore 64 home computer. 6502 or 6502-variant CPUs were used in all of Commodore's floppy disk drives for all of their 8-bit computers, from the PET line (some of which had two 6502-based CPUs) through the Commodore 128D, including the Commodore 64, and in all of Atari's disk drives for all of their 8-bit computer line, from the 400/800 through the XEGS.
Another important use of the 6500 family was in video games. The first to make use of the processor design was the Atari VCS, later renamed the Atari 2600. The VCS used a variant of the 6502 called the 6507, which had fewer pins and, as a result, could address only 8 KB of memory. Millions of the Atari consoles would be sold, each with a MOS processor. Another significant use was by the Nintendo Entertainment System and Famicom. The 6502 used in the NES was a second source version by Ricoh, a partial system-on-a-chip, that lacked the binary-coded decimal mode but added 22 memory-mapped registers and on-die hardware for sound generation, joypad reading, and sprite list DMA. Called 2A03 in NTSC consoles and 2A07 in PAL consoles (the difference being the memory divider ratio and a lookup table for audio sample rates), this processor was produced exclusively for Nintendo. The Atari Lynx used a 4 MHz version of the chip, the 65SC02.
In the 1980s, a popular electronics magazine Elektor/Elektuur used the processor in its microprocessor development board Junior Computer.
The 6502 is a little-endian 8-bit processor with a 16-bit address bus. The original versions were fabricated using an 8 µm process technology chip with a die size of 3.9 mm × 4.3 mm (advertised as 153 mils × 168 mils), for a total area of 16.6 mm2.
The internal logic runs at the same speed as the external clock rate, but despite the low clock speeds (typically in the neighborhood of 1 to 2 MHz), the 6502's performance was competitive with other contemporary CPUs using significantly faster clocks. This is partly due to a simple state machine implemented by combinational (clockless) logic to a greater extent than in many other designs; the two-phase clock (supplying two synchronizations per cycle) could thereby control the machine cycle directly. Typical instructions might take half as many cycles to complete on the 6502 as on contemporary designs. Like most simple CPUs of the era, the dynamic NMOS 6502 chip is not sequenced by a microcode ROM[clarification needed] but uses a PLA (which occupied about 15% of the chip area) for instruction decoding and sequencing. As in most 8-bit microprocessors, the chip does some limited overlapping of fetching and execution.
The low clock frequency moderated the speed requirement of memory and peripherals attached to the CPU, as only about 50% of the clock cycle was available for memory access (due to the asynchronous design, this fraction varied strongly among chip versions). This was critical at a time when affordable memory had access times in the range 250–450 ns.
Because the chip only accessed memory during certain parts of the clock cycle, and those cycles were indicated by the PHI2-low clock-out pin, other chips in a system could access memory during those times when the 6502 was off the bus. This was sometimes known as "hidden access". This technique was widely used by computer systems; they would use memory capable of access at 2 MHz, and then run the CPU at 1 MHz. This guaranteed that the CPU and video hardware could interleave their accesses, with a total performance matching that of the memory device. When faster memories became available in the 1980s, newer machines could run at higher clock rates, like the 2 MHz CPU in the BBC Micro, and still use the bus sharing techniques.
Like its precursor, the 6800, the 6502 has very few registers. The 6502's registers include one 8-bit accumulator register (A), two 8-bit index registers (X and Y), 7 processor status flag bits (P; from bit 7 to bit 0 these are the negative (N), overflow (V), reserved, break (B), decimal (D), interrupt disable (I), zero (Z) and carry (C) flag), an 8-bit stack pointer (S), and a 16-bit program counter (PC). This compares to a typical design of the same era, the Z80, which has eight general-purpose 8-bit registers, which can be combined into four 16-bit ones. The Z80 also had a complete set of alternate registers, which made a total of sixteen general-purpose registers.
In order to make up somewhat for the lack of registers, the 6502 included a zero-page addressing mode that uses one address byte in the instruction instead of the two needed to address the full 64 KB of memory. This provides fast access to the first 256 bytes of RAM by using shorter instructions. Chuck Peddle has said in interviews that the specific intention was to allow these first 256 bytes of RAM to be used like registers.
The stack address space is hardwired to memory page
$01, i.e. the address range
511). Software access to the stack is done via four implied addressing mode instructions, whose functions are to push or pop (pull) the accumulator or the processor status register. The same stack is also used for subroutine calls via the JSR (jump to subroutine) and RTS (return from subroutine) instructions and for interrupt handling.
The chip uses the index and stack registers effectively with several addressing modes, including a fast "direct page" or "zero page" mode, similar to that found on the PDP-8, that accesses memory locations from addresses 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address)—code for the 6502 uses the zero page much as code for other processors would use registers. On some 6502-based microcomputers with an operating system, the operating system uses most of zero page, leaving only a handful of locations for the user.
Addressing modes also include implied (1-byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Absolute mode is a general-purpose mode. Branch instructions use a signed 8-bit offset relative to the instruction after the branch; the numerical range −128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode uses the accumulator as an effective address and does not need any operand data. Immediate mode uses an 8-bit literal operand.
The indirect modes are useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register is added to a 16-bit base address read from zero page, which is located by a single byte following the opcode. The Y register is therefore an index register in the sense that it is used to hold an actual index (as opposed to the X register in the 6800, where a base address was directly stored and to which an immediate offset could be added). Incrementing the index register to walk the array byte-wise takes only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation is found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acts as a set of up to 128 additional (though very slow) address registers.
The 6502 is capable of performing addition and subtraction in binary or binary-coded decimal. Placing the CPU into BCD mode with the
SED (set D flag) instruction results in decimal arithmetic, in which
$99 + $01 would result in $00 and the carry (C) flag being set. In binary mode (
CLD, clear D flag), the same operation would result in $9A and the carry flag being cleared. Other than Atari BASIC, BCD mode was seldom used in home-computer applications.
See the Hello world! article for a simple but characteristic example of 6502 assembly language.
6502 instruction operation codes (opcodes) are 8 bits long and have the general form AAABBBCC, where AAA and CC define the opcode, and BBB defines the addressing mode.
For instance, consider the
ORA instruction, which performs a bitwise OR on the bits in the accumulator with another value. The instruction opcode is of the form 000bbb01, where bbb may be 010 for an immediate mode value (constant), 001 for zero-page fixed address, 011 for an absolute address, and so on.
This pattern is not absolute, and there are a number of exceptions. However, where it does apply, it allows one to easily deconstruct opcode values back to assembly mnemonics for the majority of instructions, handling the edge cases with special-purpose code.
Of the 256 possible opcodes available using an 8-bit pattern, the original 6502 uses 151 of them, organized into 56 instructions with (possibly) multiple addressing modes. Depending on the instruction and addressing mode, the opcode may require zero, one or two additional bytes for operands. Hence 6502 machine instructions vary in length from one to three bytes. The operand is stored in the 6502's customary little-endian format.
The 65C816, the 16-bit CMOS descendant of the 6502, also supports 24-bit addressing, which results in instructions being assembled with three-byte operands, also arranged in little-endian format.
The remaining 105 opcodes are undefined. In the original design, instructions where the low-order 4 bits (nibble) were 3, 7, B or F were not used, providing room for future expansion. Likewise, the $2x column had only a single entry,
LDX #constant. The remaining 25 empty slots were distributed. Some of the empty slots were used in the 65C02 to provide both new instructions and variations on existing ones with new addressing modes. The $Fx instructions were initially left free to allow 3rd-party vendors to add their own instructions, but later versions of the 65C02 standardized a set of bit fiddling instructions developed by Rockwell Semiconductor.
A 6502 assembly language statement consists of a three-character instruction mnemonic, followed by any operands. Instructions that do not take a separate operand but target a single register based on the addressing mode combine the target register in the instruction mnemonic, so the assembler uses
INX as opposed to
INC X to increment the X register.
|Opcode matrix for the 6502 instruction set|
|Addressing modes: A – accumulator, # – immediate, zpg – zero page, abs – absolute, ind – indirect, X – indexed by X register, Y – indexed by Y register, rel – relative|
|High nibble||Low nibble|
|0||BRK||ORA (ind,X)||ORA zpg||ASL zpg||PHP||ORA #||ASL A||ORA abs||ASL abs|
|1||BPL rel||ORA (ind),Y||ORA zpg,X||ASL zpg,X||CLC||ORA abs,Y||ORA abs,X||ASL abs,X|
|2||JSR abs||AND (ind,X)||BIT zpg||AND zpg||ROL zpg||PLP||AND #||ROL A||BIT abs||AND abs||ROL abs|
|3||BMI rel||AND (ind),Y||AND zpg,X||ROL zpg,X||SEC||AND abs,Y||AND abs,X||ROL abs,X|
|4||RTI||EOR (ind,X)||EOR zpg||LSR zpg||PHA||EOR #||LSR A||JMP abs||EOR abs||LSR abs|
|5||BVC rel||EOR (ind),Y||EOR zpg,X||LSR zpg,X||CLI||EOR abs,Y||EOR abs,X||LSR abs,X|
|6||RTS||ADC (ind,X)||ADC zpg||ROR zpg||PLA||ADC #||ROR A||JMP (ind)||ADC abs||ROR abs|
|7||BVS rel||ADC (ind),Y||ADC zpg,X||ROR zpg,X||SEI||ADC abs,Y||ADC abs,X||ROR abs,X|
|8||STA (ind,X)||STY zpg||STA zpg||STX zpg||DEY||TXA||STY abs||STA abs||STX abs|
|9||BCC rel||STA (ind),Y||STY zpg,X||STA zpg,X||STX zpg,Y||TYA||STA abs,Y||TXS||STA abs,X|
|A||LDY #||LDA (ind,X)||LDX #||LDY zpg||LDA zpg||LDX zpg||TAY||LDA #||TAX||LDY abs||LDA abs||LDX abs|
|B||BCS rel||LDA (ind),Y||LDY zpg,X||LDA zpg,X||LDX zpg,Y||CLV||LDA abs,Y||TSX||LDY abs,X||LDA abs,X||LDX abs,Y|
|C||CPY #||CMP (ind,X)||CPY zpg||CMP zpg||DEC zpg||INY||CMP #||DEX||CPY abs||CMP abs||DEC abs|
|D||BNE rel||CMP (ind),Y||CMP zpg,X||DEC zpg,X||CLD||CMP abs,Y||CMP abs,X||DEC abs,X|
|E||CPX #||SBC (ind,X)||CPX zpg||SBC zpg||INC zpg||INX||SBC #||NOP||CPX abs||SBC abs||INC abs|
|F||BEQ rel||SBC (ind),Y||SBC zpg,X||INC zpg,X||SED||SBC abs,Y||SBC abs,X||INC abs,X|
|Blank opcodes (e.g., F2) and all opcodes whose low nibbles are 3, 7, B and F are undefined in the 6502 instruction set.|
The processor's non-maskable interrupt (NMI) input is edge sensitive, which means that the interrupt is triggered by the falling edge of the signal rather than its level. The implication of this feature is that a wired-OR interrupt circuit is not readily supported. However, this also prevents nested NMI interrupts from occurring until the hardware makes the NMI input inactive again, often under control of the NMI interrupt handler.
The simultaneous assertion of the NMI and IRQ (maskable) hardware interrupt lines causes IRQ to be ignored. However, if the IRQ line remains asserted after the servicing of the NMI, the processor will immediately respond to IRQ, as IRQ is level sensitive. Thus a sort of built-in interrupt priority was established in the 6502 design.
The B flag is set by the 6502's periodically sampling its NMI edge detector's output and its IRQ input. The IRQ signal being driven low is only recognized though if IRQs are allowed by the I flag. If in this way a NMI request or (maskable) IRQ is detected the B flag is set to zero and causes the processor to execute the BRK instruction next instead of executing the next instruction based on the program counter.
The BRK instruction then pushes the processor status onto the stack, with the B flag bit set to zero. At the end of its execution the BRK instruction resets the B flag's value to one. This is the only way the B flag can be modified. If an instruction other than the BRK instruction pushes the B flag onto the stack as part of the processor status the B flag always has the value one.
A high-to-low transition on the SO input pin will set the processor's overflow status bit. This can be used for fast response to external hardware. For example, a high-speed polling device driver can poll the hardware once in only three cycles using a Branch-on-oVerflow-Clear (
BVC) instruction that branches to itself until overflow is set by an SO falling transition. The Commodore 1541 and other Commodore floppy disk drives use this technique to detect when the serializer is ready to transfer another byte of disk data. The system hardware and software design must ensure that an SO will not occur during arithmetic processing and disrupt calculations.
There were numerous variants of the original NMOS 6502.
|6502A||A 1.5 MHz chip used in Asteroids Deluxe.|
|6502B||Version of the 6502 capable of running at a maximum speed of 2 MHz instead of 1. The B was used in the Apple III, BBC Micro and, clocked at 1.79 MHz, early Atari 8-bit computers.|
|6502C||The “official” 6502C was a version of the original 6502 able to run at up to 4 MHz.|
|SALLY / C014806 / "6502C"||Custom 6502 variant designed for Atari, used in later Atari 8-bit computers as well as the Atari 5200 and Atari 7800 consoles.
Has a HALT signal on pin 35 and the R/W signal on pin 36 (these pins are not connected (N/C) on a standard 6502). Pulling HALT low latches the clock, pausing the processor. This was used to allow the video circuitry direct memory access (DMA).
Although sometimes referred to as "6502C" in Atari documentation, this is not the same as the "official" 6502C and the chip itself is never marked as such.
|MOS||6503||Reduced memory addressing capability (4 KB) and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).|
|MOS||6504||Reduced memory addressing capability (8 KB), no NMI, and no RDY input, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).|
|MOS||6505||Reduced memory addressing capability (4 KB) and no NMI, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted).|
|MOS||6506||Reduced memory addressing capability (4 KB), no NMI, and no RDY input, but all 3 clock pins of the 6502 (i.e. a 2-phase output clock), in a 28-pin DIP package (with the SYNC, redundant Vss, and SO pins of the 6502 also omitted).|
|MOS||6507||Reduced memory addressing capability (8 KB) and no interrupts, in a 28-pin DIP package (with the phase 1 (OUT), SYNC, redundant Vss, and SO pins of the 6502 also omitted). This chip was used in the Atari 2600 video game system.|
|MOS||6508||Has a built-in 8-bit input/output port and 256 bytes of internal static RAM.|
|MOS||6509||Can address up to 1 MB of RAM as 16 banks of 64 KB and was used in the Commodore CBM-II series.|
|MOS||6510||Has a built-in 6-bit programmable input/output port and was used in the Commodore 64. The 8500 is effectively an HMOS version of the 6510, and replaced it in later versions of the C64.|
|The MOS Technology 6512, 6513, 6514, and 6515 each rely on an external clock, instead of using an internal clock generator like the 650x (e.g. 6502). This was used to advantage in some designs where the clocks could be run asymmetrically, increasing overall CPU performance.
The 6512 is a 6502 with a 2-phase clock input for an external clock oscillator, instead of an on-board clock oscillator. The 6513, 6514 and 6515 are similarly equivalent to (respectively) a 6503, 6504 and 6505 with the same 2-phase clock input.
The 6512 was used in the BBC Micro B+64.
|Ricoh||2A03||6502 variant including an audio processing unit and lacking the BCD mode, used in the Nintendo Entertainment System.|
|System on a chip designs that utilize a complete Atari 2600 in a 48-pin DIP package.|
|WDC||65C02||CMOS version of the NMOS 6502 that was designed by Bill Mensch of the Western Design Center (WDC), featuring reduced power consumption, support for much higher clock speeds, new instructions, new addressing modes for some existing instructions, and correction of NMOS errata, such as the |
|WDC||65SC02||Variant of the WDC 65C02 without individual bit manipulation operations (RMB, SMB, BBR and BBS). This core, running at 4 MHz, was used in the Atari Lynx's main system IC.|
|CSG / MOS||65CE02||CMOS derivative developed by the Commodore Semiconductor Group (CSG), formerly MOS Technology.|
R6500/11, R6500/12, R6500/15 "One-Chip Microcomputers"
|Enhanced versions of the 6502-based processor, also including individual bit manipulation operations (RMB, SMB, BBR and BBS), on-chip 192 byte zero-page RAM, UART, etc.|
|The Rockwell R65F11 (introduced in 1983) and the later R65F12 are enhanced versions of the 6502-based processor, also including individual bit manipulation operations (RMB, SMB, BBR and BBS), on-chip zero-page RAM, on-chip Forth kernel ROM, a UART, etc.|
|GTE||G65SC102||Software compatible with the 65C02, but has a slightly different pinout and oscillator circuit. The BBC Master Turbo included the 4 MHz version of this CPU on a coprocessor card, which could also be bought separately and added to the Master 128.|
|The R65C00, R65C21, and R65C29 have two enhanced CMOS 6502s in a single chip, and the R65C00 and R65C21 additionally contained 2 KB of mask-programmable ROM.|
|CM630||A 1 MHz Eastern Bloc clone of the 6502 and was used in the Pravetz 8A and 8C, Bulgarian clones of the Apple // series.|
|Variants of the 6510 (itself an enhanced 6502), introduced in 1984. They extended the number of I/O port pins from 6 to 7, but omitted pins for non-maskable interrupt and clock output. Used in Commodore's C-16, C-116 and Plus/4 computers. The main difference between 7501 and 8501 CPUs is that the 7501 was manufactured with the HMOS-1 process and the 8501 with HMOS-2.|
|MOS||8500||Introduced in 1985 as an HMOS version of the 6510 (which is in turn based on the 6502). Other than the process modification, the 8500 is virtually identical to the NMOS version of the 6510. It replaced the 6510 in later versions of the Commodore 64.|
|MOS||8502||Designed by MOS Technology and used in the Commodore 128. Based on the MOS 6510 used in the Commodore 64, the 8502 was able run at double clock rate of the 6510. The 8502 family also includes the MOS 7501, 8500 and 8501.|
|Hudson Soft||HuC6280||Japanese video game company Hudson Soft's improved version of the WDC 65C02. Manufactured for them by Seiko Epson and NEC for the SuperGrafx. The most notable product using the HuC6280 is NEC's TurboGrafx-16 video game console.|
The Western Design Center designed and currently produces the W65C816S processor, a 16-bit, static-core successor to the 65C02. The W65C816S is a newer variant of the 65C816, which is the core of the Apple IIGS computer and is the basis of the Ricoh 5A22 processor that powers the Super Nintendo Entertainment System. The W65C816S incorporates minor improvements over the 65C816 that make the newer chip not an exact hardware-compatible replacement for the earlier one. Among these improvements was conversion to a static core, which makes it possible to stop the clock in either phase without the registers losing data. Available through electronics distributors, as of March 2020, the W65C816S is officially rated for 14 MHz operation.
The Western Design Center also designed and produced the 65C802, which was a 65C816 core with a 64-kilobyte address space in a 65(C)02 pin-compatible package. The 65C802 could be retrofitted to a 6502 board and would function as a 65C02 on power-up, operating in "emulation mode." As with the 65C816, a two-instruction sequence would switch the 65C802 to "native mode" operation, exposing its 16-bit accumulator and index registers, as well as other 65C816 features. The 65C802 was not widely used and production was discontinued.
The following 6502 assembly language source code is for a subroutine named
TOLOWER, which copies a null-terminated character string from one location to another, converting upper-case letter characters to lower-case letters. The string being copied is the "source", and the string into which the converted source is stored is the "destination".
0080 0080 00 04 0082 00 05 0600 0600 A0 00 0602 B1 80 0604 F0 11 0606 C9 41 0608 90 06 060A C9 5B 060C B0 02 060E 09 20 0610 91 82 0612 C8 0613 D0 ED 0615 38 0616 60 0617 91 82 0619 18 061A 60 061B
; TOLOWER: ; ; Convert a null-terminated character string to all lower case. ; Maximum string length is 255 characters, plus the null term- ; inator. ; ; Parameters: ; ; SRC((snd)) Source string address ; DST((snd)) Destination string address ; ORG $0080 ; SRC .WORD $0400 ;source string pointer DST .WORD $0500 ;destination string pointer ; ORG $0600 ;execution start address ; TOLOWER LDY #$00 ;starting index ; LOOP LDA (SRC),Y ;get from source string BEQ DONE ;end of string ; CMP #'A' ;if lower than UC alphabet... BCC SKIP ;copy unchanged ; CMP #'Z'+1 ;if greater than UC alphabet... BCS SKIP ;copy unchanged ; ORA #%00100000 ;convert to lower case ; SKIP STA (DST),Y ;store to destination string INY ;bump index BNE LOOP ;next character ; ; NOTE: If Y wraps the destination string will be left in an undefined ; state. We set carry to indicate this to the calling function. ; SEC ;report string too long error &... RTS ;return to caller ; DONE STA (DST),Y ;terminate destination string CLC ;report conversion completed &... RTS ;return to caller ; .END
The 6502 had several bugs and quirks, which had to be accounted for when programming it:
JMP (<address>), is partly broken. If <address> is hex xxFF (i.e., any word ending in FF), the processor will not jump to the address stored in xxFF and
xxFF+1as expected, but rather the one defined by xxFF and xx00 (for example,
JMP ($10FF)would jump to the address stored in 10FF and 1000, instead of the one stored in 10FF and 1100). This defect continued through the entire NMOS line, but was corrected in the CMOS derivatives.
The first 6502 was fabricated with 8 micron technology, ran at one megahertz and had a maximum memory of 64k.
FLAG B CONTROL; FLAG B
B_OUT; INTERNAL DATA BUS (DB)
named SALLY by Atari engineers, but [support documents call it] "6502 (Modified)", "6502 Modified", "Custom 6502", or "6502C". [..] SALLY 6502 chips are never marked "6502C" but, other than the UMC UM6502I, always [marked] C014806. [..] [Other] chips marked "6502C" [..] are NOT the Atari "6502C" but [standard 6502] certified for 4MHz
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