This article needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed.Find sources: "Heterogeneous computing" – news · newspapers · books · scholar · JSTOR (October 2014) (Learn how and when to remove this template message)
Heterogeneous computing refers to systems that use more than one kind of processor or cores. These systems gain performance or energy efficiency not just by adding the same type of processors, but by adding dissimilar coprocessors, usually incorporating specialized processing capabilities to handle particular tasks.
Usually heterogeneity in the context of computing referred instruction-set architectures (ISA), where the main processor has one and other processors have another - usually a very different - architecture (maybe more than one), not just a different microarchitecture (floating point number processing is a special case of this - not usually referred to as heterogeneous).
In the past heterogeneous computing meant different ISAs had to be handled differently, while in a modern example, Heterogeneous System Architecture (HSA) systems eliminate the difference (for the user) while using multiple processor types (typically CPUs and GPUs), usually on the same integrated circuit, to provide the best of both worlds: general GPU processing (apart from the GPU's well-known 3D graphics rendering capabilities, it can also perform mathematically intensive computations on very large data-sets), while CPUs can run the operating system and perform traditional serial tasks.
The level of heterogeneity in modern computing systems is gradually increasing as further scaling of fabrication technologies allows for formerly discrete components to become integrated parts of a system-on-chip, or SoC. For example, many new processors now include built-in logic for interfacing with other devices (SATA, PCI, Ethernet, USB, RFID, radios, UARTs, and memory controllers), as well as programmable functional units and hardware accelerators (GPUs, cryptography co-processors, programmable network processors, A/V encoders/decoders, etc.).
Recent findings show that a heterogeneous-ISA chip multiprocessor that exploits diversity offered by multiple ISAs can outperform the best same-ISA homogeneous architecture by as much as 21% with 23% energy savings and a reduction of 32% in Energy Delay Product (EDP). AMD's 2014 announcement on its pin-compatible ARM and x86 SoCs, codename Project Skybridge,
suggested a heterogeneous-ISA (ARM+x86) chip multiprocessor in the making.
Heterogeneous CPU topology
A system with heterogenous CPU topology is a system where the same ISA is used, but the cores themselves are different in speed. The setup is more similar to a symmetric multiprocessor. (Although such systems are technically asymmetric multiprocessors, the cores do not differ in roles or device access.) There are typically two types of cores: a higher performance core usually known as the "big" or P-core and a more power efficient core usually known as the "small" or E-core.
A common use of such topology is to provide better power efficiency in mobile SoCs.
- ARM big.LITTLE (succeeded by DynamIQ) is the prototypical case, where faster high-power cores are combined with slower low-power cores.
- Apple has produced Apple silicon ARM cores with similar organization.
- Intel has also produced hybrid x86-64 cores codenamed Lakefield, although not without major limitations in instruction set support. The newer Alder Lake reduces the sacrifice by adding more instruction set support to the "small" core.
Heterogeneous computing systems present new challenges not found in typical homogeneous systems. The presence of multiple processing elements raises all of the issues involved with homogeneous parallel processing systems, while the level of heterogeneity in the system can introduce non-uniformity in system development, programming practices, and overall system capability. Areas of heterogeneity can include:
- ISA or instruction-set architecture
- Compute elements may have different instruction set architectures, leading to binary incompatibility.
- ABI or application binary interface
- Compute elements may interpret memory in different ways. This may include both endianness, calling convention, and memory layout, and depends on both the architecture and compiler being used.
- API or application programming interface
- Library and OS services may not be uniformly available to all compute elements.
- Low-Level Implementation of Language Features
- Language features such as functions and threads are often implemented using function pointers, a mechanism which requires additional translation or abstraction when used in heterogeneous environments.
- Memory Interface and Hierarchy
- Compute elements may have different cache structures, cache coherency protocols, and memory access may be uniform or non-uniform memory access (NUMA). Differences can also be found in the ability to read arbitrary data lengths as some processors/units can only perform byte-, word-, or burst accesses.
- Compute elements may have differing types of interconnect aside from basic memory/bus interfaces. This may include dedicated network interfaces, Direct memory access (DMA) devices, mailboxes, FIFOs, and scratchpad memories, etc. Furthermore, certain portions of a heterogeneous system may be cache-coherent, whereas others may require explicit software-involvement for maintaining consistency and coherency.
- A heterogeneous system may have CPUs that are identical in terms of architecture, but have underlying micro-architectural differences that lead to various levels of performance and power consumption. Asymmetries in capabilities paired with opaque programming models and operating system abstractions can sometimes lead to performance predictability problems, especially with mixed workloads.
- Data Partitioning
- While partitioning data on homogeneous platforms is often trivial, it has been shown that for the general heterogeneous case, the problem is NP-Complete. For small numbers of partitions, optimal partitionings that perfectly balance load and minimize communication volume have been shown to exist. 
This section may require cleanup to meet Wikipedia's quality standards. The specific problem is: Some groupings don't make sense when "what's added compared to a bare CPU" is considered. Maybe it's time to rethink the taxonomy. Please help improve this section if you can. (September 2021) (Learn how and when to remove this template message)
Heterogeneous computing hardware can be found in every domain of computing—from high-end servers and high-performance computing machines all the way down to low-power embedded devices including mobile phones and tablets.
- High Performance Computing
- Embedded Systems (DSP and Mobile Platforms)
- Texas Instruments OMAP (Media coprocessor)
- Analog Devices Blackfin (DSP and media coprocessors)
- Qualcomm Snapdragon (GPU, DSP, image, sometimes AI coprocessor; Modem, Sensors)
- Nvidia Tegra (GPU; Modem, Sensors)
- Samsung Exynos (GPU; Modem, Sensors)
- Apple "A" series (CPU, GPU; Modem)
- Movidius Myriad Vision processing units, which includes several symmetric processors, complemented by fixed function units, and a pair of SPARC based controllers.
- HiSilicon Kirin SoCs (GPU; Modem, Sensors)
- MediaTek SoCs (GPU; Modem, Sensors)
- Cadence Design Systems Tensilica DSPs
- Reconfigurable Computing
- Intel IXP Network Processors
- Netronome NFP Network Processors
- General Purpose Computing, Gaming, and Entertainment Devices
- Intel Sandy Bridge, Ivy Bridge, and Haswell CPUs (Integrated GPU, OpenCL-capable since Ivy Bridge)
- AMD Excavator and Ryzen APUs (Integrated GPU, OpenCL-capable)
- IBM Cell, found in the PlayStation 3 (Vector coprocessor)
- Emotion Engine, found in the PlayStation 2 (Vector and media coprocessors)
- ARM big.LITTLE/DynamIQ CPU architecture (heterogenous topology)
- Nearly all ARM vendors offer heterogeneous solutions; ARM, Qualcomm, Nvidia, Apple, Samsung, HiSilicon, MediaTek, etc.