By 1988, Wei Zhang et al. had discussed fast optical implementations of convolutional neural networks for alphabet recognition.^{[14]}^{[15]}
In the 1990s, there were also attempts to create parallel high-throughput systems for workstations aimed at various applications, including neural network simulations.^{[16]}^{[17]}
FPGA-based accelerators were also first explored in the 1990s for both inference and training.^{[18]}^{[19]}
In 2014, Chen et al. proposed DianNao (Chinese for "electric brain"),^{[20]} to accelerate deep neural networks especially. DianNao provides 452 Gop/s peak performance (of key operations in deep neural networks) in a footprint of 3.02 mm^{2} and 485 mW. Later, the successors (DaDianNao,^{[21]} ShiDianNao,^{[22]} PuDianNao^{[23]}) were proposed by the same group, forming the DianNao Family^{[24]}
Heterogeneous computing incorporates many specialized processors in a single system, or a single chip, each optimized for a specific type of task. Architectures such as the Cell microprocessor^{[27]} have features significantly overlapping with AI accelerators including: support for packed low precision arithmetic, dataflow architecture, and prioritizing throughput over latency. The Cell microprocessor has been applied to a number of tasks^{[28]}^{[29]}^{[30]} including AI.^{[31]}^{[32]}^{[33]}
In the 2000s, CPUs also gained increasingly wide SIMD units, driven by video and gaming workloads; as well as support for packed low-precision data types.^{[34]} Due to the increasing performance of CPUs, they are also used for running AI workloads. CPUs are superior for DNNs with small or medium-scale parallelism, for sparse DNNs and in low-batch-size scenarios.
Graphics processing units or GPUs are specialized hardware for the manipulation of images and calculation of local image properties. The mathematical basis of neural networks and image manipulation are similar, embarrassingly parallel tasks involving matrices, leading GPUs to become increasingly used for machine learning tasks.^{[35]}^{[36]}
In 2012, Alex Krizhevsky adopted two GPUs to train a deep learning network, i.e., AlexNet,^{[37]} which won the champion of the ISLVRC-2012 competition. During the 2010s, GPU manufacturers such as Nvidia added deep learning related features in both hardware (e.g., INT8 operators) and software (e.g., cuDNN Library).
Over the 2010s GPUs continued to evolve in a direction to facilitate deep learning, both for training and inference in devices such as self-driving cars.^{[38]}^{[39]} GPU developers such as Nvidia NVLink are developing additional connective capability for the kind of dataflow workloads AI benefits from. As GPUs have been increasingly applied to AI acceleration, GPU manufacturers have incorporated neural network-specific hardware to further accelerate these tasks.^{[40]}^{[41]}Tensor cores are intended to speed up the training of neural networks.^{[41]}
GPUs continue to be used in large-scale AI applications. For example, Summit, a supercomputer from IBM for Oak Ridge National Laboratory,^{[42]} contains 27,648 Nvidia Tesla V100 cards, which can be used to accelerate deep learning algorithms.
Deep learning frameworks are still evolving, making it hard to design custom hardware. Reconfigurable devices such as field-programmable gate arrays (FPGA) make it easier to evolve hardware, frameworks, and software alongside each other.^{[43]}^{[18]}^{[19]}^{[44]}
Microsoft has used FPGA chips to accelerate inference for real-time deep learning services.^{[45]}
While GPUs and FPGAs perform far better than CPUs for AI-related tasks, a factor of up to 10 in efficiency^{[46]}^{[47]} may be gained with a more specific design, via an application-specific integrated circuit (ASIC).^{[48]} These accelerators employ strategies such as optimized memory use^{[citation needed]} and the use of lower precision arithmetic to accelerate calculation and increase throughput of computation.^{[49]}^{[50]} Some low-precision floating-point formats used for AI acceleration are half-precision and the bfloat16 floating-point format.^{[51]}^{[52]}Cerebras Systems has built a dedicated AI accelerator based on the largest processor in the industry, the second-generation Wafer Scale Engine (WSE-2), to support deep learning workloads.^{[53]}^{[54]}
In 2019, researchers from Politecnico di Milano found a way to solve systems of linear equations in a few tens of nanoseconds via a single operation. Their algorithm is based on in-memory computing with analog resistive memories which performs with high efficiencies of time and energy, via conducting matrix–vector multiplication in one step using Ohm's law and Kirchhoff's law. The researchers showed that a feedback circuit with cross-point resistive memories can solve algebraic problems such as systems of linear equations, matrix eigenvectors, and differential equations in just one step. Such an approach improves computational times drastically in comparison with digital algorithms.^{[58]}
In 2020, Marega et al. published experiments with a large-area active channel material for developing logic-in-memory devices and circuits based on floating-gatefield-effect transistors (FGFETs).^{[59]} Such atomically thin semiconductors are considered promising for energy-efficient machine learning applications, where the same basic device structure is used for both logic operations and data storage. The authors used two-dimensional materials such as semiconducting molybdenum disulphide to precisely tune FGFETs as building blocks in which logic operations can be performed with the memory elements. ^{[59]}
In 1988, Wei Zhang et al. discussed fast optical implementations of convolutional neural networks for alphabet recognition.^{[14]}^{[15]}
In 2021, J. Feldmann et al. proposed an integrated photonichardware accelerator for parallel convolutional processing.^{[60]} The authors identify two key advantages of integrated photonics over its electronic counterparts: (1) massively parallel data transfer through wavelength division multiplexing in conjunction with frequency combs, and (2) extremely high data modulation speeds.^{[60]} Their system can execute trillions of multiply-accumulate operations per second, indicating the potential of integratedphotonics in data-heavy AI applications.^{[60]} Optical processors that can also perform backpropagation for artificial neural networks have been experimentally developed.^{[61]}
As of 2016, the field is still in flux and vendors are pushing their own marketing term for what amounts to an "AI accelerator", in the hope that their designs and APIs will become the dominant design. There is no consensus on the boundary between these devices, nor the exact form they will take; however several examples clearly aim to fill this new space, with a fair amount of overlap in capabilities.
In the past when consumer graphics accelerators emerged, the industry eventually adopted Nvidia's self-assigned term, "the GPU",^{[62]}
as the collective noun for "graphics accelerators", which had taken many forms before settling on an overall pipeline implementing a model presented by Direct3D^{[clarification needed]}.
All models of Intel Meteor Lake processors have a Versatile Processor Unit (VPU) built-in for accelerating inference for computer vision and deep learning.^{[63]}
Inspired from the pioneer work of DianNao Family, many DLPs are proposed in both academia and industry with design optimized to leverage the features of deep neural networks for high efficiency. At ISCA 2016, three sessions (15%) of the accepted papers, focused on architecture designs about deep learning. Such efforts include Eyeriss (MIT),^{[64]} EIE (Stanford),^{[65]} Minerva (Harvard),^{[66]} Stripes (University of Toronto) in academia,^{[67]} TPU (Google),^{[68]} and MLU (Cambricon) in industry.^{[69]} We listed several representative works in Table 1.
The major components of DLPs architecture usually include a computation component, the on-chip memory hierarchy, and the control logic that manages the data communication and computing flows.
Regarding the computation component, as most operations in deep learning can be aggregated into vector operations, the most common ways for building computation components in digital DLPs are the MAC-based (multiplier-accumulation) organization, either with vector MACs^{[20]}^{[21]}^{[23]} or scalar MACs.^{[68]}^{[22]}^{[64]} Rather than SIMD or SIMT in general processing devices, deep learning domain-specific parallelism is better explored on these MAC-based organizations. Regarding the memory hierarchy, as deep learning algorithms require high bandwidth to provide the computation component with sufficient data, DLPs usually employ a relatively larger size (tens of kilobytes or several megabytes) on-chip buffer but with dedicated on-chip data reuse strategy and data exchange strategy to alleviate the burden for memory bandwidth. For example, DianNao, 16 16-in vector MAC, requires 16 × 16 × 2 = 512 16-bit data, i.e., almost 1024 GB/s bandwidth requirements between computation components and buffers. With on-chip reuse, such bandwidth requirements are reduced drastically.^{[20]} Instead of the widely used cache in general processing devices, DLPs always use scratchpad memory as it could provide higher data reuse opportunities by leveraging the relatively regular data access pattern in deep learning algorithms. Regarding the control logic, as the deep learning algorithms keep evolving at a dramatic speed, DLPs start to leverage dedicated ISA (instruction set architecture) to support the deep learning domain flexibly. At first, DianNao used a VLIW-style instruction set where each instruction could finish a layer in a DNN. Cambricon^{[74]} introduces the first deep learning domain-specific ISA, which could support more than ten different deep learning algorithms. TPU also reveals five key instructions from the CISC-style ISA.
Hybrid DLPs emerge for DNN inference and training acceleration because of their high efficiency. Processing-in-memory (PIM) architectures are one most important type of hybrid DLP. The key design concept of PIM is to bridge the gap between computing and memory, with the following manners: 1) Moving computation components into memory cells, controllers, or memory chips to alleviate the memory wall issue.^{[71]}^{[75]}^{[76]} Such architectures significantly shorten data paths and leverage much higher internal bandwidth, hence resulting in attractive performance improvement. 2) Build high efficient DNN engines by adopting computational devices. In 2013, HP Lab demonstrated the astonishing capability of adopting ReRAM crossbar structure for computing.^{[77]} Inspiring by this work, tremendous work are proposed to explore the new architecture and system design based on ReRAM,^{[70]}^{[78]}^{[79]}^{[71]} phase change memory,^{[75]}^{[80]}^{[81]} etc.
Benchmarks such as MLPerf and others may be used to evaluate the performance of AI accelerators.^{[82]} Table 2 lists several typical benchmarks for AI accelerators.
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^Joshua V. Dillon; Ian Langmore; Dustin Tran; Eugene Brevdo; Srinivas Vasudevan; Dave Moore; Brian Patton; Alex Alemi; Matt Hoffman; Rif A. Saurous (November 28, 2017). TensorFlow Distributions (Report). arXiv:1711.10604. Bibcode:2017arXiv171110604D. Accessed May 23, 2018. All operations in TensorFlow Distributions are numerically stable across half, single, and double floating-point precisions (as TensorFlow dtypes: tf.bfloat16 (truncated floating point), tf.float16, tf.float32, tf.float64). Class constructors have a validate_args flag for numerical asserts
^ ^{a}^{b}Chi, Ping; Li, Shuangchen; Xu, Cong; Zhang, Tao; Zhao, Jishen; Liu, Yongpan; Wang, Yu; Xie, Yuan (June 2016). "PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory". 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA). IEEE. pp. 27–39. doi:10.1109/isca.2016.13. ISBN978-1-4673-8947-1.
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^Ji, Yu Zhang, Youyang Xie, Xinfeng Li, Shuangchen Wang, Peiqi Hu, Xing Zhang, Youhui Xie, Yuan (January 27, 2019). FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture. OCLC1106329050.((cite book)): CS1 maint: multiple names: authors list (link)
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