Package on a package (PoP) is an integrated circuit packaging method to vertically combine discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed atop each other, i.e. stacked, with a standard interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras, at the cost of slightly higher height requirements. Stacks with more than 2 packages are uncommon, due to heat dissipation considerations.

Configuration

Two widely used configurations exist for PoP:

Typical logic plus memory PoP stack, common to mobile phone SoCs or baseband modems from 2005 onward
Typical logic plus memory PoP stack, common to mobile phone SoCs or baseband modems from 2005 onward

During PCB assembly, the bottom package of a PoP stack is placed directly on the PCB, and the other package(s) of the stack are stacked on top. The packages of a PoP stack become attached to each other (and to the PCB) during reflow soldering.

Benefits

The package on a package technique tries to combine the benefits of traditional packaging with the benefits of die-stacking techniques, while avoiding their drawbacks.

Traditional packaging places each die in its own package, a package designed for normal PCB assembly techniques that place each package directly on the PCB side-by-side. The 3D die-stacking system in package (SiP) techniques stacks multiple die in a single package, which has several advantages and also some disadvantages compared to traditional PCB assembly.

In embedded PoP techniques, chips are embedded in a substrate on the bottom of the package. This PoP technology enables smaller packages with shorter electrical connections and is supported by companies such as Advanced Semiconductor Engineering (ASE).[1]

Advantages over traditional isolated-chip packaging

The most obvious benefit is motherboard space savings. PoP uses much less PCB area, almost as little as stacked-die packages.

Electrically, PoP offers benefits by minimizing track length between different interoperating parts, such as a controller and memory. This yields better electrical performance of devices, since shorter routing of interconnections between circuits yields faster signal propagation and reduced noise and cross-talk.

Advantages over chip stacking

There are several key differences between stacked-die and stacked-package products.

The main financial benefit of package on a package is that the memory device is decoupled from the logic device. Therefore this gives PoP all the same advantages that traditional packaging has over stacked-die products:

JEDEC standardization

Other names

Package on a package is also known by other names:

History

Main article: Three-dimensional integrated circuit § History

In 2001, a Toshiba research team including T. Imoto, M. Matsui and C. Takubo developed a "System Block Module" wafer bonding process for manufacturing 3D integrated circuit (3D IC) packages.[4][5] The earliest known commercial use of a 3D package-on-package chip was in Sony's PlayStation Portable (PSP) handheld game console, released in 2004. The PSP hardware includes eDRAM (embedded DRAM) memory manufactured by Toshiba in a 3D package chip with two dies stacked vertically.[6] Toshiba called it "semi-embedded DRAM" at the time, before later calling it a stacked "chip-on-chip" (CoC) solution.[6][7]

In April 2007, Toshiba commercialized an eight-layer 3D chip package, the 16 GB THGAM embedded NAND flash memory chip, which was manufactured with eight stacked 2 GB NAND flash chips.[8] The same month, U.S. Patent 7,923,830 ("Package-on-package secure module having anti-tamper mesh in the substrate of the upper package") was filed by Steven M. Pope and Ruben C. Zeta of Maxim Integrated.[9] In September 2007, Hynix Semiconductor introduced 24-layer 3D packaging technology, with a 16 GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.[10]

References

  1. ^ LaPedus, Mark (2014-06-19). "Mobile Packaging Market Heats Up". Semiconductor Engineering. Retrieved 2016-04-28.
  2. ^ Thomas, Glen. "Package-on-Package Flux". Indium Corporation. Retrieved 2015-07-30.
  3. ^ Amkor Technology. "Package on Package (PoP | PSfvBGA | PSfcCSP | TMV® PoP)". Retrieved 2015-07-30.
  4. ^ Garrou, Philip (6 August 2008). "Introduction to 3D Integration". Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits (PDF). Wiley-VCH. p. 4. doi:10.1002/9783527623051.ch1. ISBN 9783527623051.
  5. ^ Imoto, T.; Matsui, M.; Takubo, C.; Akejima, S.; Kariya, T.; Nishikawa, T.; Enomoto, R. (2001). "Development of 3-Dimensional Module Package, "System Block Module"". Electronic Components and Technology Conference. Institute of Electrical and Electronics Engineers (51): 552–7.
  6. ^ a b James, Dick (2014). "3D ICs in the real world". 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014): 113–119. doi:10.1109/ASMC.2014.6846988. ISBN 978-1-4799-3944-2. S2CID 42565898.
  7. ^ "System-in-Package (SiP)". Toshiba. Archived from the original on 3 April 2010. Retrieved 3 April 2010.
  8. ^ "TOSHIBA COMMERCIALIZES INDUSTRY'S HIGHEST CAPACITY EMBEDDED NAND FLASH MEMORY FOR MOBILE CONSUMER PRODUCTS". Toshiba. April 17, 2007. Archived from the original on November 23, 2010. Retrieved 23 November 2010.
  9. ^ "United States Patent US 7,923,830 B2" (PDF). 2011-04-12. Retrieved 2015-07-30.
  10. ^ "Hynix Surprises NAND Chip Industry". Korea Times. 5 September 2007. Retrieved 8 July 2019.

Further reading