Floatingpoint formats 

IEEE 754 

Other 
Alternatives 
Computer architecture bit widths 

Bit 
Application 
Binary floatingpoint precision 
Decimal floatingpoint precision 
In computing, quadruple precision (or quad precision) is a binary floatingpoint–based computer number format that occupies 16 bytes (128 bits) with precision at least twice the 53bit double precision.
This 128bit quadruple precision is designed not only for applications requiring results in higher than double precision,^{[1]} but also, as a primary function, to allow the computation of double precision results more reliably and accurately by minimising overflow and roundoff errors in intermediate calculations and scratch variables. William Kahan, primary architect of the original IEEE 754 floatingpoint standard noted, "For now the 10byte Extended format is a tolerable compromise between the value of extraprecise arithmetic and the price of implementing it to run fast; very soon two more bytes of precision will become tolerable, and ultimately a 16byte format ... That kind of gradual evolution towards wider precision was already in view when IEEE Standard 754 for FloatingPoint Arithmetic was framed."^{[2]}
In IEEE 7542008 the 128bit base2 format is officially referred to as binary128.
The IEEE 754 standard specifies a binary128 as having:
This gives from 33 to 36 significant decimal digits precision. If a decimal string with at most 33 significant digits is converted to the IEEE 754 quadrupleprecision format, giving a normal number, and then converted back to a decimal string with the same number of digits, the final result should match the original string. If an IEEE 754 quadrupleprecision number is converted to a decimal string with at least 36 significant digits, and then converted back to quadrupleprecision representation, the final result must match the original number.^{[3]}
The format is written with an implicit lead bit with value 1 unless the exponent is stored with all zeros. Thus only 112 bits of the significand appear in the memory format, but the total precision is 113 bits (approximately 34 decimal digits: log_{10}(2^{113}) ≈ 34.016). The bits are laid out as:
The quadrupleprecision binary floatingpoint exponent is encoded using an offset binary representation, with the zero offset being 16383; this is also known as exponent bias in the IEEE 754 standard.
Thus, as defined by the offset binary representation, in order to get the true exponent, the offset of 16383 has to be subtracted from the stored exponent.
The stored exponents 0000_{16} and 7FFF_{16} are interpreted specially.
Exponent  Significand zero  Significand nonzero  Equation 

0000_{16}  0, −0  subnormal numbers  (−1)^{signbit} × 2^{−16382} × 0.significandbits_{2} 
0001_{16}, ..., 7FFE_{16}  normalized value  (−1)^{signbit} × 2^{exponentbits2 − 16383} × 1.significandbits_{2}  
7FFF_{16}  ±∞  NaN (quiet, signalling) 
The minimum strictly positive (subnormal) value is 2^{−16494} ≈ 10^{−4965} and has a precision of only one bit. The minimum positive normal value is 2^{−16382} ≈ 3.3621 × 10^{−4932} and has a precision of 113 bits, i.e. ±2^{−16494} as well. The maximum representable value is 2^{16384} − 2^{16271} ≈ 1.1897 × 10^{4932}.
These examples are given in bit representation, in hexadecimal, of the floatingpoint value. This includes the sign, (biased) exponent, and significand.
0000 0000 0000 0000 0000 0000 0000 0001_{16} = 2^{−16382} × 2^{−112} = 2^{−16494} ≈ 6.4751751194380251109244389582276465525 × 10^{−4966} (smallest positive subnormal number)
0000 ffff ffff ffff ffff ffff ffff ffff_{16} = 2^{−16382} × (1 − 2^{−112}) ≈ 3.3621031431120935062626778173217519551 × 10^{−4932} (largest subnormal number)
0001 0000 0000 0000 0000 0000 0000 0000_{16} = 2^{−16382} ≈ 3.3621031431120935062626778173217526026 × 10^{−4932} (smallest positive normal number)
7ffe ffff ffff ffff ffff ffff ffff ffff_{16} = 2^{16383} × (2 − 2^{−112}) ≈ 1.1897314953572317650857593266280070162 × 10^{4932} (largest normal number)
3ffe ffff ffff ffff ffff ffff ffff ffff_{16} = 1 − 2^{−113} ≈ 0.9999999999999999999999999999999999037 (largest number less than one)
3fff 0000 0000 0000 0000 0000 0000 0000_{16} = 1 (one)
3fff 0000 0000 0000 0000 0000 0000 0001_{16} = 1 + 2^{−112} ≈ 1.0000000000000000000000000000000001926 (smallest number larger than one)
c000 0000 0000 0000 0000 0000 0000 0000_{16} = −2
0000 0000 0000 0000 0000 0000 0000 0000_{16} = 0 8000 0000 0000 0000 0000 0000 0000 0000_{16} = −0
7fff 0000 0000 0000 0000 0000 0000 0000_{16} = infinity ffff 0000 0000 0000 0000 0000 0000 0000_{16} = −infinity
4000 921f b544 42d1 8469 898c c517 01b8_{16} ≈ π
3ffd 5555 5555 5555 5555 5555 5555 5555_{16} ≈ 1/3
By default, 1/3 rounds down like double precision, because of the odd number of bits in the significand.
So the bits beyond the rounding point are 0101...
which is less than 1/2 of a unit in the last place.
A common software technique to implement nearly quadruple precision using pairs of doubleprecision values is sometimes called doubledouble arithmetic.^{[4]}^{[5]}^{[6]} Using pairs of IEEE doubleprecision values with 53bit significands, doubledouble arithmetic provides operations on numbers with significands of at least^{[4]} 2 × 53 = 106 bits (actually 107 bits^{[7]} except for some of the largest values, due to the limited exponent range), only slightly less precise than the 113bit significand of IEEE binary128 quadruple precision. The range of a doubledouble remains essentially the same as the doubleprecision format because the exponent has still 11 bits,^{[4]} significantly lower than the 15bit exponent of IEEE quadruple precision (a range of 1.8 × 10^{308} for doubledouble versus 1.2 × 10^{4932} for binary128).
In particular, a doubledouble/quadrupleprecision value q in the doubledouble technique is represented implicitly as a sum q = x + y of two doubleprecision values x and y, each of which supplies half of q's significand.^{[5]} That is, the pair (x, y) is stored in place of q, and operations on q values (+, −, ×, ...) are transformed into equivalent (but more complicated) operations on the x and y values. Thus, arithmetic in this technique reduces to a sequence of doubleprecision operations; since doubleprecision arithmetic is commonly implemented in hardware, doubledouble arithmetic is typically substantially faster than more general arbitraryprecision arithmetic techniques.^{[4]}^{[5]}
Note that doubledouble arithmetic has the following special characteristics:^{[8]}
In addition to the doubledouble arithmetic, it is also possible to generate tripledouble or quaddouble arithmetic if higher precision is required without any higher precision floatingpoint library. They are represented as a sum of three (or four) doubleprecision values respectively. They can represent operations with at least 159/161 and 212/215 bits respectively.
A similar technique can be used to produce a doublequad arithmetic, which is represented as a sum of two quadrupleprecision values. They can represent operations with at least 226 (or 227) bits.^{[9]}
Quadruple precision is often implemented in software by a variety of techniques (such as the doubledouble technique above, although that technique does not implement IEEE quadruple precision), since direct hardware support for quadruple precision is, as of 2016, less common (see "Hardware support" below). One can use general arbitraryprecision arithmetic libraries to obtain quadruple (or higher) precision, but specialized quadrupleprecision implementations may achieve higher performance.
A separate question is the extent to which quadrupleprecision types are directly incorporated into computer programming languages.
Quadruple precision is specified in Fortran by the real(real128)
(module iso_fortran_env
from Fortran 2008 must be used, the constant real128
is equal to 16 on most processors), or as real(selected_real_kind(33, 4931))
, or in a nonstandard way as REAL*16
. (Quadrupleprecision REAL*16
is supported by the Intel Fortran Compiler^{[10]} and by the GNU Fortran compiler^{[11]} on x86, x8664, and Itanium architectures, for example.)
For the C programming language, ISO/IEC TS 186613 (floatingpoint extensions for C, interchange and extended types) specifies _Float128
as the type implementing the IEEE 754 quadrupleprecision format (binary128).^{[12]} Alternatively, in C/C++ with a few systems and compilers, quadruple precision may be specified by the long double type, but this is not required by the language (which only requires long double
to be at least as precise as double
), nor is it common.
On x86 and x8664, the most common C/C++ compilers implement long double
as either 80bit extended precision (e.g. the GNU C Compiler gcc^{[13]} and the Intel C++ Compiler with a /Qlong‑double
switch^{[14]}) or simply as being synonymous with double precision (e.g. Microsoft Visual C++^{[15]}), rather than as quadruple precision. The procedure call standard for the ARM 64bit architecture (AArch64) specifies that long double
corresponds to the IEEE 754 quadrupleprecision format.^{[16]} On a few other architectures, some C/C++ compilers implement long double
as quadruple precision, e.g. gcc on PowerPC (as doubledouble^{[17]}^{[18]}^{[19]}) and SPARC,^{[20]} or the Sun Studio compilers on SPARC.^{[21]} Even if long double
is not quadruple precision, however, some C/C++ compilers provide a nonstandard quadrupleprecision type as an extension. For example, gcc provides a quadrupleprecision type called __float128
for x86, x8664 and Itanium CPUs,^{[22]} and on PowerPC as IEEE 128bit floatingpoint using the mfloat128hardware or mfloat128 options;^{[23]} and some versions of Intel's C/C++ compiler for x86 and x8664 supply a nonstandard quadrupleprecision type called _Quad
.^{[24]}
Zig provides support for it with its f128
type.^{[25]}
Google's workinprogress language Carbon provides support for it with the type called 'f128'.^{[26]}
__float128
and __complex128
operations.__float128
and _Quad
types, and includes a custom implementation of the standard math library.^{[27]}IEEE quadruple precision was added to the IBM System/390 G5 in 1998,^{[31]} and is supported in hardware in subsequent z/Architecture processors.^{[32]}^{[33]} The IBM POWER9 CPU (Power ISA 3.0) has native 128bit hardware support.^{[23]}
Native support of IEEE 128bit floats is defined in PARISC 1.0,^{[34]} and in SPARC V8^{[35]} and V9^{[36]} architectures (e.g. there are 16 quadprecision registers %q0, %q4, ...), but no SPARC CPU implements quadprecision operations in hardware as of 2004^{[update]}.^{[37]}
NonIEEE extendedprecision (128 bits of storage, 1 sign bit, 7 exponent bits, 112 fraction bits, 8 bits unused) was added to the IBM System/370 series (1970s–1980s) and was available on some System/360 models in the 1960s (System/36085,^{[38]} 195, and others by special request or simulated by OS software).
The Siemens 7.700 and 7.500 series mainframes and their successors support the same floatingpoint formats and instructions as the IBM System/360 and System/370.
The VAX processor implemented nonIEEE quadrupleprecision floating point as its "H Floatingpoint" format. It had one sign bit, a 15bit exponent and 112fraction bits, however the layout in memory was significantly different from IEEE quadruple precision and the exponent bias also differed. Only a few of the earliest VAX processors implemented H Floatingpoint instructions in hardware, all the others emulated H Floatingpoint in software.
The NEC Vector Engine architecture supports adding, subtracting, multiplying and comparing 128bit binary IEEE 754 quadrupleprecision numbers.^{[39]} Two neighboring 64bit registers are used. Quadrupleprecision arithmetic is not supported in the vector register.^{[40]}
The RISCV architecture specifies a "Q" (quadprecision) extension for 128bit binary IEEE 7542008 floatingpoint arithmetic.^{[41]} The "L" extension (not yet certified) will specify 64bit and 128bit decimal floating point.^{[42]}
Quadrupleprecision (128bit) hardware implementation should not be confused with "128bit FPUs" that implement SIMD instructions, such as Streaming SIMD Extensions or AltiVec, which refers to 128bit vectors of four 32bit singleprecision or two 64bit doubleprecision values that are operated on simultaneously.