This article contains general information about field-programmable gate array (FPGA) devices from Xilinx, based on official specifications.

Terminology

The fields in the table listed below describe the following:

• Model – The marketing name for the device, assigned by Xilinx.
• Launch – Date when the product was announced.
• Sub-models – Some FPGA models have multiple sub-models.
• Flip-Flops (K) – The number of flip-flops embedded within the FPGA fabric.
• LUTs (K) – The number of lookup tables embedded within the FPGA fabric.
• DSP Slices – The number of digital signal processor slices embedded within the FPGA fabric.
• Peak DSP Performance (GMAC/s) – The maximum number of multiply-accumulate operations per second that can be performed by the digital signal processors that are embedded within the FPGA fabric. This is a theoretical best-case number.
• PCIe – Bus by which the device is attached to an external system.
• Max Distributed RAM (Mb) – Random Access Memory within the LUTs.^[1]
• Total Block RAM (Mb) – On-chip RAM that is not integrated within the LUTs.
• UltraRAM (Mb) – An additional block of RAM that was introduced with the Zynq UltraScale+ FPGA line. UltraRAM can be powered down for extended periods of time.^[2]

Model naming

The model name of most devices has some indication of its size, but the exact scheme used has varied over time:

• The first Xilinx device, the XC2064, is named after the 64 CLBs it contains
• After that, Xilinx started including a rough approximation of device capacity in equivalent gate count (which is measured by synthesizing a large benchmark design corpus to both a standard gate library and to a given FPGA device, then deriving an approximate conversion factor from that):
  • XC2018 and all XC3000 devices use the gate count divided by 100 (ie. XC3020 is considered a rough equivalent of 2000 gates)^[3]
  • XC4000, XC5200, XC6200, Spartan, Spartan-II, Spartan-3 (all kinds), Virtex, and Virtex-II (except for Virtex-II Pro) devices use the gate count divided by 1000 (ie. XC4003 is considered roughly equivalent to 3000 gates, XC3S5000 is considered roughly equivalent to 5 million gates). However, the device families differ in whether they use the low bound, average, or high bound of the conversion factor for the model name (eg. XC4003 uses the average of the estimated 2000-5000 gate range listed in the datasheet, while the functionally identical XCS05 uses the high bound of this range).
• Virtex-II Pro and Virtex-4 devices instead started using an "equivalent logic cells" metric divided by 1000 (XC4VLX60 is considered to be an equivalent of 60000 logic cells). The logic cell is, nominally, a simple 4-input LUT paired with a flip-flop. The logic count is obtained by multiplying the LUT count of the device by an arbitrary effectiveness factor of 1.125 to account for the extra capacity of the hard CLB logic compared to a bare LUT.^[4]
• Virtex-5/6, Spartan-6, and 7 Series (not including Zynq-7000) continue using the same metric, but the effectiveness factor has been updated to 1.6, because of the upgrade from 4-input LUTs to 6-input LUTs.
• UltraScale devices initially used the same "equivalent logic cells" metric, but divided by 10000 for the model name (ie. XCVU440 is considered to be equivalent to 4400000 logic cells), and with the effectiveness factor updated to 1.75 because of CLB upgrades. However, for marketing reasons, later versions of UltraScale data sheets instead started measuring device capacity in a new metric called "system logic cells", using an inflated conversion factor of 2.1875. This makes the model names seemingly unrelated to any device capacity measurements listed in the current data sheets.^[5]
• Zynq-7000, UltraScale+, and Versal devices abandon the idea of directly embedding logic capacity in the model name, assigning the names more or less arbitrarily.

Series overview

Note: The process information for early FPGA devices (before Virtex) may be inaccurate, due to the devices being subject to die shrink without changing the model name — the process listed above may not be the only process in which a given device has been manufactured.

Early FPGA devices

XC2000

The XC2000 devices have the following user-programmable blocks:^[25]

• CLBs (Configurable Logic Blocks): each CLB consists of two 3-input LUTs, a hard multiplexer combining LUT outputs (which can be used to combine them to a single 4-input LUT, among other things) and one flip-flop (with asynchronous set and reset capabilities)
• User I/O blocks: each user I/O pin is associated with an I/O block, which consists of an input buffer, an input flip-flop, and a tri-state output buffer
• One crystal oscillator amplifier
• Two global clock buffers

Note: the available user I/O amount varies with chip packaging.

XC3000

The XC3000 devices have the following user-programmable blocks:^[26]

• CLBs (Configurable Logic Blocks): each CLB consists of two 4-input LUTs, a hard multiplexer combining LUT outputs (which can be used to combine them to a single 5-input LUT, among other things) and two flip-flops (with asynchronous set or reset capabilities)
• User I/O blocks: each user I/O pin is associated with an I/O block, which consists of an input buffer, an input flip-flop, a tri-state output buffer, and an output flip-flop
• Intra-FPGA tri-state buses, with tri-state buffers
• One crystal oscillator amplifier
• Two global clock buffers

Note: the available user I/O amount varies with chip packaging.

XC4000, Spartan

The XC4000 and Spartan devices have the following user-programmable blocks:^{[27][28][29][30]}

• CLBs (Configurable Logic Blocks), each CLB containing:
  • two 4-input LUTs (F and G), which can be used as distributed RAM in 16×2 bit or 32×1 bit configurations (except on XC4000D devices)
  • a 3-input LUT (H) that can combine F and G outputs (for example, to implement a 5-input LUT)
  • two flip-flops (with clock enable and asynchronous set or reset)
  • carry chain logic
• User I/O blocks, one for each user I/O pin:
  • input buffer
  • tri-state output buffer
  • programmable pull-up or pull-down
  • input flip-flop (except on XC4000H devices)
  • output flip-flop (except on XC4000H devices)
  • optional delay element
  • fast capture latch (on some devices)
  • output multiplexer (on some devices)
• Edge decoders (essentially wide AND gates)
• Intra-FPGA tri-state buses, with tri-state buffers
• Global clock buffers
• Miscellaneous configuration logic (startup and readback control, boundary scan logic allowing custom user JTAG opcodes)

Note: the available user I/O amount varies with chip packaging.

XC5200

The XC5200 devices have the following user-programmable blocks:^[31]

• CLBs (Configurable Logic Blocks): each CLB consists of 4 LCs (logic cells). Each logic cell consists of one 4-input LUT, a carry chain multiplexer, and one flip-flop (with clock enable and asynchronous reset). The CLB also has two dedicated multiplexers that can combine outputs of adjacent LCs (which can be used, among other purposes, to effectively combine the two 4-input LUTs into a 5-input LUT)
• User I/O blocks: each user I/O pin is associated with an I/O block, which consists of an input buffer and a tri-state output buffer
• Intra-FPGA tri-state buses, with tri-state buffers
• One crystal oscillator amplifier
• Four global clock buffers, one in each corner
• Miscellaneous configuration logic (startup and readback control, boundary scan logic allowing custom user JTAG opcodes)

Note: the available user I/O amount varies with chip packaging.

XC6200

The XC6200 family is unusual in several ways:^[32]

• as opposed to other early FPGAs where a design always takes up the whole device and is synthesized once, then usually stored in flash storage, XC6200 is dynamically reconfigurable in arbitrarily small chunks (down to a single logic cell), and is meant to be used along with an external CPU that can modify parts of design in real time
• the logic is not LUT based; instead, every logic cell consists of a 2-to-1 MUX whose inputs can be inverted or tied to constants (to implement arbitrary 2-input logic function) and a flip-flop
• the routing structure is fully documented, unusually simple, and hierarchical in nature, with the device made of 16×16 cell tiles and 4×4 cell blocks
• the configuration data format is likewise fully documented in the data sheet,^[32] allowing (and encouraging) users to create logic designs without using vendor tools
• the part of configuration RAM that corresponds to unused area of circuit is explicitly allowed to be used for unrelated data storage

XC8100

The XC8100 family is unusual in several ways:^[32]

• The configuration storage is made of one-time programmable antifuses, as opposed to other FPGAs (which use RAM cells and need to have configuration reuploaded upon power-up) and to CPLDs (which use non-volatile but multiple time programmable EPROM/EEPROM/flash storage).
• The logic is not LUT based; instead, the device is made of logic cells, which have 4 general inputs (+1 cascade input), 1 general output (+1 cascade output) and can be configured as either an AND gate or a sum-of-products, whose inputs can be inverted or tied to constants. This arrangement allows, as special cases, construction of a 2-input MUX or a D latch within a single cell, or combining two cells configured as D latches to construct a D flip-flop.

Virtex, Spartan-II

The Virtex and Spartan-II devices are made of the following user-programmable blocks:

• CLBs (configurable logic blocks), each made of two mostly-independent SLICEs, where a SLICE contains:
  • two 4-input LUTs, which can also be used as 16-bit distributed RAMs (which can be combined into 16×2 or 32×1 single-port or 16×1 dual port arrangements), or as 16-bit shift registers (which can be cascaded together to make longer shift registers)
  • carry chain logic consisting of two MUXCY+XORCY cell pairs, for construction of efficient ALUs or wide logic functions
  • two MULT_AND cells, to be combined with MUXCY+XORCY for construction of efficient multipliers
  • two hard multiplexer cells (MUXF5 and MUXF6) that can combine the LUT outputs together, allowing for efficient multiplexer tree construction or for construction of wider LUTs (5-input LUT out of two 4-input LUTs, or 6-input LUT out of four 4-input LUTs)
  • two flip-flops with clock enable and (configurable as synchronous or asynchronous) set and reset inputs; they can also be used as latches
• Intra-FPGA tri-state buses with tri-state buffers (two buffers per CLB)
• 4kbit true dual port block RAMs, which can be used in 4096×1, 2048×2, 1024×4, 512×8, or 256×16 configurations
• IOBs (I/O blocks), one per user I/O pin, containing:
  • several kinds of input buffer (selectable by user):
    • plain CMOS input buffer
    • differential input buffer using a VREF (voltage reference) pin for advanced I/O standards
    • (Virtex-E and Spartan-IIE only) differential input buffer using a pair of I/O pins for differential I/O standards (which has to be selected from a predefined list of pairs — each IOB has its associated other IOB that can be used to construct a differential pair)
  • tristate output buffer
  • configurable pull-up, pull-down, or keeper circuit
  • three flip-flops (for input, output, tristate enable), identical to the ones in CLBs
• the IOBs are grouped into 8 I/O banks (2 for each edge of the device), with each bank having a separate power supply, allowing for usage of several I/O standards with conflicting voltage requirements in a single device
• DLLs (delay-locked loops) that can be used to phase-align, deskew, and phase-shift incoming clock signals
• 4 global clock buffers
• miscellaneous configuration logic (startup control, readback data capture, JTAG control)

The Virtex and Spartan-II devices are functionally identical to each other and differ only in available size range, performance, and packaging options. The Spartan-IIE devices use the same die as the corresponding Virtex E devices, but have some block RAM and DLLs disabled.

Note: the available user I/O amount varies with chip packaging. Additionally, not all I/Os can be used as part of a differential pair, so the available differential pair count can be smaller than half of the available I/O count.

Virtex-II

The Virtex-II devices are made of the following user-programmable blocks:

• CLBs (configurable logic blocks), which contain 4 logic SLICEs, which are an improved version of the Virtex SLICE, with the following differences:
  • when used as distributed RAM, the LUTs of multiple SLICEs within a CLB can be combined to obtain the following RAM configurations:
    • 16×1 single port (half SLICE)
    • 16×2 single port (one SLICE)
    • 32×1 single port (one SLICE)
    • 64×1 single port (two SLICEs)
    • 128×1 single port (four SLICEs)
    • 16×1 dual port (two half-SLICEs — utilizes one LUT of two different SLICEs each)
    • 16×2 dual port (two SLICEs)
    • 32×1 dual port (two SLICEs)
    • 64×1 dual port (four SLICEs)
  • the wide function multiplexers can now be used in a 4-level tree (as opposed to a 2-level tree on Virtex), allowing for construction of up to 8-input LUTs (out of 16 4-input LUTs from two neighbouring CLBs)
  • the carry chain has been enhanced with the addition of an ORCY cell allowing for efficient sum-of-products mapping
• 18kbit true dual port block RAMs, which can be used in 16386×1, 8192×2, 4096×4, 2048×9, 1024×18, 512×36 configurations (with the narrow configurations having only 16kbit available, since they cannot access the parity bits)
• hard multiplier blocks (two signed 18-bit inputs, 36-bit output) — always exactly one per block RAM, since they reside in a shared tile
• IOBs (I/O blocks), one per user I/O pin, which are an improved version of the Virtex IOB with the following differences:
  • the three I/O flip-flops are replaced with pairs of flip-flops for DDR (double data rate) capability
  • new DCI (Digitally Controlled Impedance) functionality — the device has a per-bank circuit that can utilize an external precision resistor pair connected to user I/O pins to calibrate I/O resistance on remaining user pins, providing very good impedance matching
  • support for multiple new I/O standards, including native differential I/O
• DCMs (digital clock managers), which replace Virtex DLLs, adding frequency synthesis and clock divider capability
• 16 global clock buffers
• Miscellaneous configuration logic (startup control, readback data capture, JTAG control, and the ICAP — Internal Configuration Access Port). The ICAP can be used to dynamically reprogram parts of the FPGA after the initial configuration from within the FPGA itself.

Virtex-II Pro devices include some additional blocks:

• RocketIO transceivers: high-speed parallel-to-serial transmitters and serial-to-parallel receivers with clock data recovery and 8b/10b encoders/decoders. They have a speed range of 600 Mb/s to 3.125 Gb/s and parallel width of 8, 16, or 32 bits (or 10, 20, 40 bits in 8b10b bypass mode)
• RocketIO X transceivers: improved transceivers with 64b/66b encoding/decoding (in addition to 8b/10b), speed range of 2.488 Gb/s to 6.25 Gb/s (XC2VPX20) or fixed speed of 4.25 Gb/s (XC2VPX70), and parallel width of 8, 16, 32, or 64 bits (or 10, 20, 40, 80 bits in 8b/10b bypass mode)
• Embedded PPC405 cores

Note: the available user I/O and multi-gigabit transceiver amount varies with chip packaging.

Note: the CLB count for Virtex-II Pro devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.

Spartan-3

The Spartan-3 devices are made of:

• CLBs (configurable logic blocks), which are very similar to Virtex-II, with some modifications:
  • Only two of the four SLICEs in the CLB can now be used as distributed RAM or shift registers. The SLICEs that can be used as distributed RAM or shift registers are called SLICEMs, and the remaining SLICEs are called SLICELs.
  • The available distributed RAM configurations are now:
    • 16×1 single port (half SLICEM)
    • 16×2 single port (one SLICEM)
    • 32×1 single port (one SLICEM)
    • 64×1 single port (two SLICEMs)
    • 16×1 double port (one SLICEM)
    • 32×1 double port (two SLICEMs)
  • The ORCY cell has been removed
• 18kbit true dual port block RAMs, with the following variants:
  • Spartan-3, Spartan-3E: identical to Virtex-II
  • Spartan-3A, Spartan-3AN: adds per-byte write enable signals
  • Spartan-3A DSP: like Spartan-3A, plus adds optional output pipeline registers (for faster clock-to-out time)
• hard multiplier blocks or DSP cells:
  • Spartan-3: MULT18X18, identical to Virtex-II
  • Spartan-3E, Spartan-3A, Spartan-3AN: MULT18X18SIO, adds extra input registers for faster pipelined operation
  • Spartan-3A DSP: DSP48A, a complete DSP ALU consisting of an 18×18 multiplier plus 48-bit accumulator
• IOBs (I/O blocks), one per user pin:
  • Spartan-3: similar to Virtex-II, arranged in 8 banks
  • Spartan-3E: simplified version, removes DCI capability, arranged in 4 banks (one for each device edge)
  • Spartan-3A, Spartan-3AN, Spartan-3A DSP: like Spartan-3E, but with support for newer I/O standards, and with somewhat differing capabilities of top/bottom banks and left/right banks
• DCMs, similar to Virtex-II
• 8 (Spartan-3) or 24 (Spartan-3E, 3A, 3AN, 3A DSP) global clock buffers
• Miscellaneous configuration logic (like Virtex-II, but with disabled ICAP access)
• Spartan-3A, 3AN, 3A DSP only: access to a unique device serial number (so-called device DNA)
• Spartan-3AN only: access port to the in-package SPI flash

Note: the available user I/O amount varies with chip packaging. Additionally, not all I/Os can be used as part of a differential pair, so the available differential pair count can be smaller than half of the available I/O count.

Note: for families other than Spartan-3, the CLB grid is irregular and includes holes for block RAMs and DCMs, so the CLB count is not a simple multiplication of columns×rows

Virtex-4

The Virtex-4 devices are made of:^[44][45]

• CLBs (configurable logic blocks), almost unchanged from Spartan-3
• 18kbit true dual port block RAMs, very similar to Spartan-3A DSP, but with some new capabilities:
  • two adjacent block RAMs can be combined to make a 32768×1 RAM
  • each block RAM can be used in FIFO mode (in 4096×4, 2048×9, 1024×18, 512×36 configurations) where address inputs are replaced with hardware FIFO counter functionality
• DSP48 blocks,^[46] ALU blocks with 18×18 multiplier and 48-bit accumulator
• IOBs (I/O blocks, one per user pin): in addition to Virtex-II capabilities, they support ISERDES and OSERDES blocks which do simple serial-to-parallel and parallel-to-serial conversion (2, 3, 4, 5, 6, 7, or 8 bit wide in SDR mode; 4, 6, 8, or 10 bit wide in DDR mode)
• IOBs are arranged into I/O banks; in a change from earlier FPGAs with fixed bank number, number of I/O banks on Virtex-4 varies with device size, but banks now have a more uniform size of 16 or 32 I/O pins, with the exception of special bank 0 that contains dedicated configuration pins. Each bank has two or four I/O clock buffers for fast clocks used by the SERDES blocks.
• DCMs, similar to Virtex-II/Spartan-3
• PMCDs (phase-matched clock dividers), an unusual clock divider block
• 32 global clock buffers
• Multiple clock regions, with 2 regional clock buffers per region
• Miscellaneous configuration logic: like Virtex-II, plus:
  • configuration data ECC checking circuitry
  • 32-bit user data access port

The Virtex-4 FX devices additionally contain:

• RocketIO multi-gigabit transceivers with a speed range of 622 Mb/s to 6.5 Gb/s and parallel width of 8, 16, 32, or 64 bits (10, 20, 40, or 80 bits in 8b/10b bypass mode)
• Embedded PPC405 cores
• Embedded gigabit ethernet MAC blocks (two per PPC core)

Note: the I/O banks count includes special bank 0, which contains only dedicated configuration I/O (no user I/O)

Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.

Note: the CLB count for FX devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.

Virtex-5

The Virtex-5 devices are made of:^[47][48]

• CLBs (configurable logic blocks) with a new, 6-input-LUT based construction:
  • every CLB is made of two SLICEs — either two SLICELs or one SLICEL and one SLICEMs; the exact proportion of SLICEMs in a device varies, but at least 50% of CLBs contain a SLICEM (with a higher proportion on DSP-heavy devices)
  • every SLICE contains four 6-input LUTs, each of which can be used as:
    • a 6-input LUT
    • two 5-input LUTs with shared inputs (ie. the LUT is fracturable)
    • (SLICEM only) 32×2 or 64×1 distributed RAM, which can be combined with other distributed RAMs within the same SLICEM
    • (SLICEM only) 16-bit or 32-bit shift register, which can be combined with other shift registers within the same SLICEM, for maximum of 128-bit shift register in a single SLICEM
  • the arrangement of distributed RAMs within the SLICEM is quite complex and only some configurations can be obtained; the SLICEM usage combinations allowed by vendor tools are:
    • 32×8, 64×4, 128×2, or 256×1 single port RAM
    • 32×4, 62×2, 128×1 dual port RAM
    • 32×2, 64×1 quad port RAM
    • 32×6, 64×3 simple dual port RAM
  • every SLICE contains four flip-flops with clock enable and (configurable as synchronous or asynchronous) set and reset inputs; they can also be used as latches
  • every SLICE contains a carry chain, identical in functionality to the one used since Virtex (made of MUXCY and XORCY cells), but now represented as a single CARRY4 cell for the whole SLICE (mostly for more accurate timing simulation)
  • compared to Virtex-4 SLICEs, the MULT_AND cell is gone; however, its functionality can be trivially replicated by using one half of the corresponding now-fracturable LUT
  • every SLICE contains a two-level tree of wide LUT multiplexers that can be used to combine the outputs of the LUTs, and can eg. combine the four LUTs within a SLICE into a single 8-input LUT
• 36kbit splittable true dual port block RAMs, with some new capabilities compared to Virtex-4:
  • the base block RAM is twice the size of Virtex-4; however, any given block RAM can be split into two 18kbit halves functioning independently (but only one half can use the hardware FIFO mode)
  • the available true dual port configurations of the full (36kbit) block RAM are: 32768×1, 16384×2, 8192×4, 4096×9, 2048×18, 1024×36, plus a special 65536×1 mode obtained by combining two adjacent RAMs
  • the available true dual port configurations of the half (18kbit) block RAM are: 16384×1, 8192×2, 4096×4, 2048×9, 1024×18
  • in addition to true dual port mode, the block RAMs can also be used in simple dual port mode, which doubles the maximum width of the block RAM, allowing for 512×72 (full block RAM) and 512×36 (half block RAM) configurations
  • a hardware 64-bit SECDED ECC encoder/decoder has been added, which can be used with the simple dual port mode of the full block RAM to obtain a 512×64 block RAM with error correction and detection
• DSP48E blocks,^[49] improved version of Virtex-4 DSP48 blocks with 25×18 multiplier, 48-bit accumulator (with new bitwise operations function), and pattern detector
• IOBs (I/O blocks, one per user pin): with minor improvements from Virtex-4 (mainly new I/O standard support)
• The I/O bank arrangement is similar to Virtex-4, but the banks have size of 20 or 40 user I/O pins
• CMTs (clock management tiles), each of which has:
  • two DCMs (similar to Virtex-4 DCM)
  • one PLL, which has similar general functionality as the old DCM, but is made of analog circuitry and has different set of available outputs
• the Virtex-4 PMCDs are gone; some of their functionality can be replicated by using PLLs instead
• 32 global clock buffers
• multiple clock regions, with two regional clock buffers per region
• a single system monitor: an analog-to-digital converter used for monitoring FPGA supply voltages, temperature, and possibly other, external analog signals
• Miscellaneous configuration logic: like Virtex-4, plus:
  • unique device serial number access (identical to the DNA port in Spartan-3A)
  • read-only access to user-programmable efuses
• (LXT and SXT devices) GTP^[50] multi-gigabit transceivers with a speed range of 100 Mb/s to 3.75 Gb/s and parallel width of 8, or 16 bits (10 or 20 bits in 8b/10b bypass mode)
• (FXT and TXT devices) GTX^[51] multi-gigabit transceivers with a speed range of 150 Mb/s to 6.5 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 bits in 8b/10b bypass mode)
• (FXT devices) embedded PPC440 cores
• (LXT, SXT, FXT, TXT devices) embedded gigabit Ethernet MAC cores
• (LXT, SXT, FXT, TXT devices) embedded PCI Express cores capable of Gen1.1 ×8 operation

Note: the I/O banks count includes special bank 0, which contains only dedicated configuration I/O (no user I/O)

Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.

Note: the CLB count for FXT devices is no longer a simple columns×rows multiplication, as the CLB grid contains holes for the PowerPC cores.

Virtex-6

The Virtex-6 devices are made of:^[52]

• CLBs (configurable logic blocks):^[53] like the Virtex-5 CLBs, with some minor modifications:
  • every SLICE now contains 8 flip-flops (two for each 6-LUT) instead of 4
  • the flip-flops now have only one set/reset input (ie. it is impossible to have a flip-flop with both a set and a reset input)
• 36 Kibit splittable true dual port block RAM:^[54] a slightly improved version of the Virtex-5 block RAM
• DSP48E1 blocks,^[55] upgraded version of Virtex-5 DSP48E, adding a pre-adder block
• IOBs (I/O blocks, one per user pin):^[56] with minor improvements from Virtex-5 (mainly new I/O standard support), and with notable removal of 3.3 V I/O support (max supported I/O voltage is 2.5V)
• The I/O bank arrangement is similar to Virtex-5, but the banks have constant size of 40 user I/O pins
• CMTs (clock management tiles),^[57] each of which contains two MMCMs (mixed-mode clocking managers), which are analog-based replacements for the old DCMs, and are an evolution of the Virtex-5 PLLs
• 32 global clock buffers
• multiple clock regions, with two or four regional clock buffers per region
• a single system monitor, like Virtex-5
• Miscellaneous configuration logic: like Virtex-5
• (non-LX devices) GTX multi-gigabit transceivers with a speed range of 480 Mb/s to 6.6 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 bits in 8b/10b bypass mode)
• (some HXT devices) GTH multi-gigabit transceivers with a speed range of 2.488 Gb/s to 11.2 Gb/s and parallel width of 8, 16, 32, or 64 bits (10, 20, 40, or 80 bits in 8b/10b bypass mode)
• (non-LX devices) embedded gigabit Ethernet MAC cores
• (non-LX devices) embedded PCI Express cores capable of Gen2 ×8 operation

Note: the I/O banks count does not include special bank 0, which contains only dedicated configuration I/O (no user I/O)

Note: the available user I/O, I/O bank, and multi-gigabit transceiver amount varies with chip packaging.

Note: Virtex-6 CLB grid is irregular and contains holes (for configuration center and PCI Express blocks), and so the CLB count is no longer a simple columns×rows multiplication

Note: The CXT devices use an identical die to the corresponding LXT devices, but with some disabled blocks and reduced performance (GTX transceivers have a speed range of 150 Mb/s to 3.75 Gb/s).

Spartan-6

The Spartan-6 devices are basically Spartan-3A DSP devices upgraded with some Virtex-6 technology. They are made of:^[59]

• CLBs (configurable logic blocks),^[60] similar to Virtex-6, but with some changes:
  • SLICEs now come in three types: SLICEX, SLICEL, SLICEM; SLICEX is a bare-bones version of SLICEL (wide LUT multiplexers and carry chain have been removed, only LUTs and flip-flops remain)
  • every CLB contains two SLICEs: either one SLICEX + one SLICEL, or one SLICEX + one SLICEM; around 50% of the CLBs contain a SLICEM
• 18kbit true dual port block RAMs,^[61] similar to Spartan-3A DSP, but with additional capabilities:
  • the full 18kbit block RAM can be split into two 9kbit halves, with available configurations of 8192×1, 4096×2, 2048×4, 1024×9, 512×18
  • in split mode, the half block RAMs additionally support a simple dual port mode in 256×36 configuration
• DSP48A1 blocks,^[62] which are an upgraded version of the DSP48A blocks of Spartan-3A DSP devices
• IOBs (I/O blocks, one per user pin):^[63]
  • the electrical capabilities are similar to Spartan-3A (though with new I/O standards supported); there is no DCI support, but user can select an uncalibrated I/O impedance from several settings
  • Virtex-6-like ISERDES and OSERDES blocks are present (though with fewer capabilities than Virtex-6 devices), with associated fast I/O block buffers
  • the I/O bank arrangement is similar to Spartan-3A devices, but with a minor change: small devices have 4 banks (one for each device edge), while large devices have 6 banks (with the left and right edges split into two banks
• MCBs (memory controller blocks),^[64] hard memory controllers supporting DDR, DDR2, DDR3, and LPDDR memory
• CMTs (clock management tiles),^[65] each of which has:
  • two DCMs, similar to Spartan-3A DCMs, but with new clock generator mode and dynamic reconfiguration capabilities
  • one PLL, similar to Virtex-5 PLLs
• 16 global clock buffers
• multiple clock regions, with 16 regional clock buffers each, which can replace the corresponding global clock buffer output for that region
• Miscellaneous configuration logic: like Spartan-3A, plus circuitry performing live configuration memory scanning with CRC error detection (but no correction)
• (SXT devices only) GTP multi-gigabit transceivers^[66] with speed ranges of 614 Mb/s to 810 Mb/s, 1.22 Gb/s to 1.62 Gb/s, and 2.45 Gb/s to 3.125 Gb/s, 8b/10b encoder and decoder, and parallel width of 8, 16, or 32 bits (10, 20, or 40 bits in 8b/10b bypass mode)
• (SXT devices only) embedded PCI Express cores capable of Gen1.1 ×1 operation

7 Series

The 7 series devices are made of:^[67]

• CLBs (configurable logic blocks), functionally identical to Virtex-6
• 36kbit splittable true dual port block RAM, functionally identical to Virtex-6
• DSP48E1 blocks, functionally identical to Virtex-6
• IOBs (I/O blocks, one per user pin):^[68] derived from Virtex-6, but with multiple changes:
  • the IOBs now come in two kinds
    • HR (high range) I/O, which once again supports I/O voltage up to 3.3V, but has no DCI support
    • HP (high performance) I/O, which supports I/O voltage up to 1.8V, with DCI support
  • the I/O banks now have 50 I/O pins each, as follows:
    • 24 differential I/O pairs, split into 4 "byte groups" of 6 I/O pairs (or 12 I/O pins)
    • 2 single I/O pins without differential pair
  • the CMTs (clock management tiles)^[69] are now tightly coupled with I/O banks: there is one CMT for every I/O bank, and it contains:
    • one MMCM, similar to Virtex-6 MMCM
    • one PLL, which is a version of MMCM with less advanced functionality
    • four input and four output asynchronous FIFOs, designed for memory controller usage, but available for any application
    • undocumented phaser circuitry used only by the Xilinx memory controller IPs
• global clock buffers (usually 32 of them, but some devices have only 16, and 3D devices have 32 for every die)
• multiple clock regions, with 4 regional clock buffers per region
• (not on the smallest Spartan devices) a single XADC analog-to-digital converter, which is an improved and renamed version of Virtex-6 system monitor
• Miscellaneous configuration logic: like Virtex-6

Depending on exact device family, devices may also contain some special blocks:

• GTP multi-gigabit transceivers,^[70] with speed range of 500 Mb/s to 6.6 Gb/s and parallel width of 8 or 16 bits (10 or 20 in 8b/10b bypass mode)
• GTX multi-gigabit transceivers,^[71] with speed range of 500 Mb/s to 12.5 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 in 8b/10b bypass mode)
• GTH multi-gigabit transceivers, with speed range of 500 Mb/s to 13.1 Gb/s and parallel width of 8, 16, or 32 bits (10, 20, or 40 in 8b/10b bypass mode)
• GTZ multi-gigabit transceivers, with speed range of up to 28.05 Gb/s and parallel width of up to 128 bits (160 in 8b/10b bypass mode). The GTZ transceivers, when present, reside on a separate die from the main FPGA. The documentation for GTZ transceivers is not publicly available, being restricted to members of Xilinx GTZ Lounge.
• embedded PCI Express cores capable of Gen2 ×8 operation
• embedded PCI Express cores capable of Gen3 ×8 operation
• (Zynq-7000 devices) a PS (processing system) block,^[72] containing a system on chip based on ARM Cortex-A9

Note: many 7 series devices are actually software-limitted versions of larger devices:^[74] for example, XC7A35T is the exact same die as XC7A50T, with the same geometry and block count, but the Xilinx development tools artificially limit device usage to the limits in the table above. Such software-limitted devices have very different behavior from "full" devices when nearing full utilization: a design that would have utilized 90% of XC7A50T resources will most likely fail to route (or succeed with very suboptimal performance), since the place&route tool will have very little space to optimally arrange blocks and will likely run out of routing resources due to suboptimal placement. However, an XC7A35T design that utilizes even 100% of its resources will almost certainly route with no performance degradation, as it is far from the real hardware limits, and the placer has full freedom to utilize any subset of the available blocks as long as the total used CLB/DSP/block RAM count is within the allowed software limit. The software-enforced limits are marked with * in the above table.

Note: some Spartan-7 devices are identical to some Artix-7 devices, but with disabled transceivers. However, this is different from the above software-enforced usage limit: the transceivers cannot be used anyway, as their power and I/O pads are not bonded out to device pins in the packaging.

Note: the Artix-7 devices use the same PCI Express block as Kintex-7 devices, with Gen2×8 support, but they can only be used in at most Gen2×4 configuration due to GTP transceiver limitations.

Note: several devices have smaller max User I/Os count than the I/O bank count would imply. This means that the device is not available in any packaging that actually bonds out the complete set of pads.

UltraScale and UltraScale+

The UltraScale devices are made of:^[75]

• CLBs (configurable logic blocks), which are a modified version of the 7 Series CLB:
  • every CLB now contains exactly one SLICE, which can be a SLICEM or a SLICEL
  • every SLICE now contains 8 6-input LUTs, 16 flip-flops, a carry chain, and 3-level tree of wide LUT multiplexers, making it roughly equivalent to two 7 Series SLICEs (and retaining the rough logic capacity of a single CLB)
  • because of the higher wide LUT multiplexer tree, the LUTs within a SLICE can now be combined up to a single 9-input LUT
  • the available distributed RAM combinations within a SLICEM are now:
    • 32×16, 64×8, 128×4, 256×2, 512×1 single port RAM
    • 32×8, 64×4, 128×2, 256×1 dual port RAM
    • 32×4, 64×2, 128×1 quad port RAM
    • 32×2, 64×1 octal port RAM
    • 32×14, 64×7 simple dual port RAM
• 36kbit splittable true dual block RAMs, with some minor upgrades compared to 7 Series
• DSP48E2 blocks, with some minor upgrades compared to 7 Series DSP48E1 blocks
• I/O banks with CMTs: with major changes from 7 Series^[76]
  • banks still come in HR and HP kinds
  • each bank has 52 I/O pins: 24 differential pairs, and 4 unpaired pins
  • the bank is split into 4 byte groups, each made of 6 differential pairs and one unpaired pin
  • each byte group is further split into a lower nibble (with 3 differential pairs) and upper nibble (with 3 differential pairs and one unpaired pin)
  • the ISERDES/OSERDES blocks are replaced with BITSLICE blocks; there is one TX BITSLICE and one RX bitslice for every pin, plus an additional TX bitslice for every nibble that can control the tristate signal for all pins in a nibble
  • each bank has a CMT, with one MMCM and two PLLs
  • added MIPI D-PHY support
• much more complex, distributed global clock network split into clock regions
• system monitors, which is once again a renamed version of 7 Series XADC. There is one system monitor per FPGA die (ie. multi-die FPGAs have multiple system monitors).
• Miscellaneous configuration logic
• GTH multi-gigabit transceivers with speed up to 16.3 Gb/s and parallel width of 16, 32, or 64 bits (20, 40, or 80 bits in 8b/10b bypass mode)
• (on some devices) GTY multi-gigabit transceivers with speed up to 30.5 Gb/s and parallel width of 16, 32, 64, or 128 bits (20, 40, 80, or 160 bits in 8b/10b bypass mode)
• embedded PCI Express cores capable of Gen3 ×8 operation
• (on some devices) 100 Gigabit Ethernet MAC
• (on some devices) embedded Interlaken core

The UltraScale+ devices have a few differences:

• HR banks no longer exist, being replaced with a new kind of I/O banks: HD (High Density) banks, which are very different to HR banks:
  • 24 pins (12 differential pairs) per bank
  • no CMT
  • no SERDES or BITSLICE blocks; the only logic available is simple flip-flops or DDR registers
• upgraded MMCM and PLL
• upgraded GTH transceivers
• upgraded GTY transceivers with speed up to 32.75 Gb/s
• some devices have GTM transceivers with speed up to 58.0 Gb/s (using PAM4 encoding) and parallel width of 16, 32, 64, or 128 bits (20, 40, 80, or 160 bits in 8b/10b bypass mode)
• new PCI Express cores:
  • PCIE4 core capable of Gen3 ×16 or Gen4 ×8 operation
  • PCIE4C core, additionally capable of CCIX protocol
• some devices have new UltraRAM blocks, which are true dual port 288kbit RAMs, in 4096×72 configuration

Zynq UltraScale+ devices are ARM Cortex-A53 based systems on chip sharing a die with an FPGA. The SoC part of the device is called a Processing System (PS). Each model of Zynq UltraScale+ MPSoC is available in up to 3 sub-models: CG, EG, and EV. The main differences among these sub-models are in the CPU and GPU configurations.^[77] Zynq UltraScale+ RFSoC devices are available in DR sub-models, which have PS capabilities identical to MPSoC EG sub-models.

Zynq UltraScale+ devices have some additional blocks:

• (some RFSoC devices) SD-FEC cores
• (some RFSoC devices) Digital Front End subsystem (a set of hard logic blocks for RF signal processing)
• (RFSoC devices) high-speed (radio frequency) analog-to-digital converters (RF-ADC) and digital-to-analog converters (RF-DAC), for 5G applications
• (MPSoC EV devices) a video codec unit (VCU) performing H.264 and H.265 decoding/encoding

Note: the clock region grid is irregular on some UltraScale+ devices because of a hole in bottom for the Processing System (and possibly the VCU).

Versal

In 2018, Xilinx announced a product line called Versal.^[78] Versal chips contain CPU, GPU, DSP, and FPGA components. Versal is fabricated using 7nm process technology.

The Versal devices are made of:^[79]

• PMC (Platform Management Controller), a MicroBlaze-based processor block responsible for booting the device and monitoring its operations
• PS (Processing System), an ARM system on a chip block with dual core Cortex-A72 (APU) and dual-core Cortex-R5F (RPU)
• (on some devices) CPM, a hard PCI Express block with CCIX support; comes in Gen4 and Gen5 version
• (on some devices) XRAM, a single 32Mbit block of static RAM
• a NoC (Network on Chip) spanning the device, with AXI4 interface blocks, connecting the PS, the CPM, the FPGA, the DDRMC cores, and the AI cores together
• one or more DDRMC (DDR memory controller) blocks
• (on some devices) HBM memory controller blocks
• XPIO I/O banks, which are the successor to UltraScale+ HP I/O banks; in a departure from previous devices, the XPIO banks are considered to be outside the FPGA part, and some XPIO banks can only be used by the DDRMC blocks (without FPGA connectivity)
• GTY transceivers, which can be used by the FPGA or by the CPM
• GTYP transceivers, which are a minor improvement of GTY transceivers
• GTM transceivers
• the FPGA fabric with:
  • configurable logic blocks (CLBs), which are quite different to previous architectures
    • a CLB is made of 4 SLICEs: 2 SLICELs and 2 SLICEMs
    • each SLICE still contains 8 6-input LUTs, each fracturable into two 5-input LUTs with shared inputs
    • each slice still contains 16 flip-flops, two for each LUT
    • there are no more wide LUT multiplexers
    • the carry chain has been replaced with new carry and cascade logic
    • the distributed RAM configurations are different
  • 36kbit true dual port block RAMs, with some changes from UltraScale+
  • 288kbit UltraRAM blocks, with some changes from UltraScale+
  • DSP58 blocks, which replace the old DSP48* blocks; two adjacent DSP58 blocks can be combined into a single DSP58_CPLX block, performing complex arithmetic
  • HD I/O blocks, similar to UltraScale+
    • now with 11 differential pairs (22 pins) per block
  • NoC master access ports
  • NoC slave access ports
  • hard IP blocks:
    • PCI Express Gen4 and Gen5 cores
    • MRMAC (Multirate Ethernet MAC), usable in 1×100Gbit, 2×50Gbit, 1×40Gbit, 4×25Gbit, 4×10Gbit configurations
    • DCMAC (600G Channelized Multirate Ethernet Subsystem), usable in 1×400Gbit, 3×200Gbit, 6×100Gbit configurations
    • 600Gbit Interlaken block, usable in 12×56.42Gbit, 24×28.21Gbit, or 24×12.5Gbit configurations
    • 400Gbit HSC (High-Speed Crypto) Engine, usable in 1×400Gbit, 2×200Gbit, or 4×100Gbit configurations
    • VDE (Video Decoder Engine)
• (on some devices) AI Engines, vector processor cores meant for machine learning usage
• (on some devices) AI-ML Engines, updated version of the AI Engines

Alveo and Kria

In addition to standalone FPGA chips, Xilinx also offers the Alveo product line of ready-to-use FPGA-based accelerator boards, and the Kria product line of FPGA-based Systems-on-Module (SOMs). The FPGAs used on these boards reuse the same die as standalone chips, but are considered to be distinct products by the Vivado toolchain.

FPGAs without integrated CPUs

Artix

Kintex