ARM Cortex-A72
General information
Designed byARM Holdings
L1 cache80 KiB (48 KiB I-cache with parity, 32 KiB D-cache with ECC) per core
L2 cache512 KiB to 4 MiB
L3 cacheNone
Architecture and classification
Technology node16 nm
Instruction setARMv8-A
Physical specifications
  • 1–4 per cluster, multiple clusters[1]
Products, models, variants
Product code
  • Maya
PredecessorARM Cortex-A57
SuccessorARM Cortex-A73

The ARM Cortex-A72 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings' Austin design centre. The Cortex-A72 is a 3-way decode out-of-order superscalar pipeline.[1] It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC). The Cortex-A72 was announced in 2015 to serve as the successor of the Cortex-A57, and was designed to use 20% less power or offer 90% greater performance.[2][3]



See also


  1. ^ a b "Cortex-A72 Processor". ARM Holdings. Retrieved 2014-02-02.
  2. ^ Frumusanu, Andrei (3 February 2015). "ARM Announces Cortex-A72, CCI-500, and Mali-T880". Anandtech. Retrieved 29 March 2017.
  3. ^ Frumusanu, Andrei (23 April 2015). "ARM Reveals Cortex-A72 Architecture Details". Anandtech. Retrieved 29 March 2017.
  4. ^ "Raspberry Pi 4 on sale now from $35". Raspberry Pi. 2019-06-24. Retrieved 2019-06-24.