18:53, 16 February 2006Ignaciomellatalkcontribs uploaded File:Electrostatic p.jpg(Electrostatic Precipitators Electrostatic Precipitator Electrostatic Precipitators use electrostatic forces to separate dust particles from exhaust gases. A number of high-voltage, direct-current discharge electrodes are placed between grounded collecti)
18:52, 16 February 2006Ignaciomellatalkcontribs uploaded File:SCyclone.jpg( Centrifugal collectors use cyclonic action to separate dust particles from the gas stream. In a typical cyclone, the dust gas stream enters at an angle and is spun rapidly. The centrifugal force created by the circular flow throws the dust particles to)
18:50, 16 February 2006Ignaciomellatalkcontribs uploaded File:Image 005.jpg (Commonly known as baghouses, fabric collectors use filtration to separate dust particulates from dusty gases. They are one of the most efficient and cost effective types of dust collectors available and can achieve a collection efficiency of more than 99)
11:35, 16 February 2006Ignaciomellatalkcontribs uploaded File:Dust collector.jpg(Dust collection. A typical coal dust collection system includes pickup hoods, ducting, branch lines, dust collector, fan, and a dust return system. Experience has shown that the pickup hoods and ducting design are more problematic than the fan and dust co)
16:40, 15 May 2005Ignaciomellatalkcontribs uploaded File:Inrush.gif (The inrush current of a 9000 HP motor and pump that requires almost 11 seconds to start. Most motors achieve standard operating speed within a few seconds or less, but because this motor/pump represents a very large mass, a considerable amount of time is)
16:18, 15 May 2005Ignaciomellatalkcontribs uploaded File:Dogleg2.gif (However, the routing architecture above is not the routing architecture that is actually implemented by SRAM-based FPGAs. As shown below, commercial SRAM-based FPGAs normally place a buffer between routing tracks and the input pins to which they can conne)
16:17, 15 May 2005Ignaciomellatalkcontribs uploaded File:Dogleg1.gif (Much of the prior research on FPGA routing architectures has assumed that input pin doglegs are possible. An input pin dogleg occurs when one connects more than one routing wire segment to the same logic block input pin. The input pin dogleg then, allows)
15:40, 15 May 2005Ignaciomellatalkcontribs uploaded File:Segmentation.gif (Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below)
15:32, 15 May 2005Ignaciomellatalkcontribs uploaded File:Switch box.gif (Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. (In term)
15:25, 15 May 2005Ignaciomellatalkcontribs uploaded File:Logic block pins.gif (The FPGA logic block consists of a 4-input look-up table (LUT), and a flip flop, as shown below. There is only one output, which can be either the registered or the unregistered LUT output. The logic block has four inputs for the LUT and a clock input. Si)
15:24, 15 May 2005Ignaciomellatalkcontribs uploaded File:Fpga structure.gif (The FPGA is an array or island-style FPGA. It consists of an array of logic blocks and routing channels. Two I/O pads fit into the height of one row or the width of one column, as shown below. All the routing channels have the same width (number of wires))
15:23, 15 May 2005Ignaciomellatalkcontribs uploaded File:F c.gif (Each logic block input pin can connect to any one of the wiring segments in the channel adjacent to it. Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. (In the usual FPGA terminology, then, Fc = the nu)