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Racetrack memory or domain-wall memory (DWM) is an experimental non-volatile memory device under development at IBM's Almaden Research Center by a team led by physicist Stuart Parkin.[1] In early 2008, a 3-bit version was successfully demonstrated.[2] If it were to be developed successfully, racetrack memory would offer storage density higher than comparable solid-state memory devices like flash memory.[citation needed]


Racetrack memory uses a spin-coherent electric current to move magnetic domains along a nanoscopic permalloy wire about 200 nm across and 100 nm thick. As current is passed through the wire, the domains pass by magnetic read/write heads positioned near the wire, which alter the domains to record patterns of bits. A racetrack memory device is made up of many such wires and read/write elements. In general operational concept, racetrack memory is similar to the earlier bubble memory of the 1960s and 1970s. Delay-line memory, such as mercury delay lines of the 1940s and 1950s, are a still-earlier form of similar technology, as used in the UNIVAC and EDSAC computers. Like bubble memory, racetrack memory uses electrical currents to "push" a sequence of magnetic domains through a substrate and past read/write elements. Improvements in magnetic detection capabilities, based on the development of spintronic magnetoresistive sensors, allow the use of much smaller magnetic domains to provide far higher bit densities.

In production, it was expected[citation needed] that the wires could be scaled down to around 50 nm. There were two arrangements considered for racetrack memory. The simplest was a series of flat wires arranged in a grid with read and write heads arranged nearby. A more widely studied arrangement used U-shaped wires arranged vertically over a grid of read/write heads on an underlying substrate. This would allow the wires to be much longer without increasing its 2D area, although the need to move individual domains further along the wires before they reach the read/write heads results in slower random access times. Both arrangements offered about the same throughput performance. The primary concern in terms of construction was practical; whether or not the three dimensional vertical arrangement would be feasible to mass-produce.

Comparison to other memory devices

Projections in 2008 suggested that racetrack memory would offer performance on the order of 20-32 ns to read or write a random bit. This compared to about 10,000,000 ns for a hard drive, or 20-30 ns for conventional DRAM. The primary authors discussed ways to improve the access times with the use of a "reservoir" to about 9.5 ns. Aggregate throughput, with or without the reservoir, would be on the order of 250-670 Mbit/s for racetrack memory, compared to 12800 Mbit/s for a single DDR3 DRAM, 1000 Mbit/s for high-performance hard drives, and 1000 to 4000 Mbit/s for flash memory devices. The only current technology that offered a clear latency benefit over racetrack memory was SRAM, on the order of 0.2 ns, but at a higher cost. Larger feature size "F" of about 45 nm (as of 2011) with a cell area of about 140 F2.[3][4]

Racetrack memory is one among several emerging technologies that aim to replace conventional memories such as DRAM and Flash, and potentially offer a universal memory device applicable to a wide variety of roles. Other contenders included magnetoresistive random-access memory (MRAM), phase-change memory (PCRAM) and ferroelectric RAM (FeRAM). Most of these technologies offer densities similar to flash memory, in most cases worse, and their primary advantage is the lack of write-endurance limits like those in flash memory. Field-MRAM offers excellent performance as high as 3 ns access time, but requires a large 25-40 F² cell size. It might see use as an SRAM replacement, but not as a mass storage device. The highest densities from any of these devices is offered by PCRAM, with a cell size of about 5.8 F², similar to flash memory, as well as fairly good performance around 50 ns. Nevertheless, none of these can come close to competing with racetrack memory in overall terms, especially density. For example, 50 ns allows about five bits to be operated in a racetrack memory device, resulting in an effective cell size of 20/5=4 F², easily exceeding the performance-density product of PCM. On the other hand, without sacrificing bit density, the same 20 F² area could fit 2.5 2-bit 8 F² alternative memory cells (such as resistive RAM (RRAM) or spin-torque transfer MRAM), each of which individually operating much faster (~10 ns).

In most cases, memory devices store one bit in any given location, so they are typically compared in terms of "cell size", a cell storing one bit. Cell size itself is given in units of F², where "F" is the feature size design rule, representing usually the metal line width. Flash and racetrack both store multiple bits per cell, but the comparison can still be made. For instance, hard drives appeared to be reaching theoretical limits around 650 nm²/bit,[5] defined primarily by the capability to read and write to specific areas of the magnetic surface. DRAM has a cell size of about 6 F², SRAM is much less dense at 120 F². NAND flash memory is currently the densest form of non-volatile memory in widespread use, with a cell size of about 4.5 F², but storing three bits per cell for an effective size of 1.5 F². NOR flash memory is slightly less dense, at an effective 4.75 F², accounting for 2-bit operation on a 9.5 F² cell size.[4] In the vertical orientation (U-shaped) racetrack, nearly 10-20 bits are stored per cell, which itself would have a physical size of at least about 20 F². In addition, bits at different positions on the "track" would take different times (from ~10 to ~1000 ns, or 10 ns/bit) to be accessed by the read/write sensor, because the "track" would move the domains at a fixed rate of ~100 m/s past the read/write sensor.

Development challenges

One limitation of the early experimental devices was that the magnetic domains could be pushed only slowly through the wires, requiring current pulses on the orders of microseconds to move them successfully. This was unexpected, and led to performance equal roughly to that of hard drives, as much as 1000 times slower than predicted. Recent research has traced this problem to microscopic imperfections in the crystal structure of the wires which led to the domains becoming "stuck" at these imperfections. Using an X-ray microscope to directly image the boundaries between the domains, their research found that domain walls would be moved by pulses as short as a few nanoseconds when these imperfections were absent. This corresponds to a macroscopic performance of about 110 m/s.[6]

The voltage required to drive the domains along the racetrack would be proportional to the length of the wire. The current density must be sufficiently high to push the domain walls (as in electromigration). A difficulty for racetrack technology arises from the need for high current density (>108 A/cm²); a 30 nm x 100 nm cross-section would require >3 mA. The resulting power draw becomes higher than that required for other memories, e.g., spin-transfer torque memory (STT-RAM) or flash memory.

Another challenge associated with Racetrack memory is the stochastic nature in which the domain walls move, i.e., they move and stop at random positions.[7] There have been attempts to overcome this challenge by producing notches at the edges of the nanowire.[8] Researchers have also proposed staggered nanowires to pin the domain walls precisely.[9] Experimental investigations have shown[10] the effectiveness of staggered domain wall memory.[11] Recently researchers have proposed non-geometrical approaches such as local modulation of magnetic properties through composition modification. Techniques such as annealing induced diffusion[12] and ion-implantation[13] are used.

See also


  1. ^ Spintronics Devices Research, Magnetic Racetrack Memory Project
  2. ^ Masamitsu Hayashi et al. (April 2008). "Current-Controlled Magnetic Domain-Wall Nanowire Shift Register". Science. 320 (5873): 209–211. Bibcode:2008Sci...320..209H. doi:10.1126/science.1154587. PMID 18403706. S2CID 7872869.((cite journal)): CS1 maint: uses authors parameter (link)
  3. ^ "ITRS 2011". Retrieved 8 November 2012.
  4. ^ a b Parkin; et al. (11 April 2008). "Magnetic Domain-Wall Racetrack Memory". Science. 320 (5873): 190–4. Bibcode:2008Sci...320..190P. doi:10.1126/science.1145799. PMID 18403702. S2CID 19285283.
  5. ^ 1 Tbit/in² is approx. 650nm²/bit.
  6. ^ Swarup, Amarendra (11 May 2007). "'Racetrack' memory could gallop past the hard disk". New Scientist.
  7. ^ Kumar, D.; Jin, T.; Risi, S. Al; Sbiaa, R.; Lew, W. S.; Piramanayagam, S. N. (March 2019). "Domain Wall Motion Control for Racetrack Memory Applications". IEEE Transactions on Magnetics. 55 (3): 2876622. Bibcode:2019ITM....5576622K. doi:10.1109/TMAG.2018.2876622. hdl:10356/139037. ISSN 0018-9464. S2CID 67872687.
  8. ^ Hayashi, M.; Thomas, L.; Moriya, R.; Rettner, C.; Parkin, S. S. P. (2008). "Current-Controlled Magnetic Domain-Wall Nanowire Shift Register". Science. 320 (5873): 209–211. Bibcode:2008Sci...320..209H. doi:10.1126/science.1154587. ISSN 0036-8075. PMID 18403706. S2CID 7872869.
  9. ^ Mohammed, H. (2020). "Controlled spin-torque driven domain wall motion using staggered magnetic wires". Applied Physics Letters. 116 (3): 032402. arXiv:1908.09304. Bibcode:2020ApPhL.116c2402M. doi:10.1063/1.5135613. S2CID 201695574.
  10. ^ Prem Piramanayagam (24 February 2019), Staggered Domain Wall Memory, archived from the original on 21 December 2021, retrieved 13 March 2019
  11. ^ Al Bahri, M.; Borie, B.; Jin, T.L.; Sbiaa, R.; Kläui, M.; Piramanayagam, S.N. (8 February 2019). "Staggered Magnetic Nanowire Devices for Effective Domain-Wall Pinning in Racetrack Memory". Physical Review Applied. 11 (2): 024023. Bibcode:2019PhRvP..11b4023A. doi:10.1103/PhysRevApplied.11.024023. hdl:10220/48230. S2CID 139224277.
  12. ^ Jin, T. L.; Ranjbar, M.; He, S. K.; Law, W. C.; Zhou, T. J.; Lew, W. S.; Liu, X. X.; Piramanayagam, S. N. (2017). "Tuning magnetic properties for domain wall pinning via localized metal diffusion". Scientific Reports. 7 (1): 16208. Bibcode:2017NatSR...716208J. doi:10.1038/s41598-017-16335-z. PMC 5701220. PMID 29176632.
  13. ^ Jin, Tianli; Kumar, Durgesh; Gan, Weiliang; Ranjbar, Mojtaba; Luo, Feilong; Sbiaa, Rachid; Liu, Xiaoxi; Lew, Wen Siang; Piramanayagam, S. N. (2018). "Nanoscale Compositional Modification in Co/Pd Multilayers for Controllable Domain Wall Pinning in Racetrack Memory". Physica Status Solidi RRL. 12 (10): 1800197. Bibcode:2018PSSRR..1200197J. doi:10.1002/pssr.201800197. hdl:10356/137507. S2CID 52557582.