|Computer memory and data storage types|
Electrochemical Random-Access Memory (ECRAM) is a type of non-volatile memory (NVM) with multiple levels per cell (MLC) designed for deep learning analog acceleration. An ECRAM cell is a three-terminal device composed of a conductive channel, an insulating electrolyte, an ionic reservoir, and metal contacts. The resistance of the channel is modulated by ionic exchange at the interface between the channel and the electrolyte upon application of an electric field. The charge-transfer process allows both for state retention in the absence of applied power, and for programming of multiple distinct levels, both differentiating ECRAM operation from the one of a field-effect transistor (FET). The write operation is deterministic and can result in symmetrical potentiation and depression, making ECRAM arrays attractive for acting as artificial synaptic weights in physical implementations of artificial neural networks (ANN). The technology challenges include open circuit potential (OCP) and semiconductor foundry compatibility associated with energy materials. Universities, government laboratories, and corporate research teams have contributed to the development of ECRAM for analog computing. Notably, Sandia National Laboratories designed a lithium-based cell inspired by solid-state battery materials, Stanford University built an organic proton-based cell, and International Business Machines (IBM) demonstrated in-memory selector-free parallel programming for a logistic regression task in an array of metal-oxide ECRAM designed for insertion in the back end of line (BEOL).
Stress to the gate, relative to channel electrodes, can be applied in the form of fixed current or bias, driving ions toward - or away from - the electrolyte/channel interface where charge transfer occurs with free carriers. Upon insertion in the channel, the ionic charge is neutralized and the atomic species intercalate or bind to the conductive host matrix, in some cases yielding strain and localized phase transformation. Such reversible processes are equivalent to anodic/cathodic reactions in battery cells or electrochromic devices. Although in ECRAM, the programming of the memory element is defined not as a change in capacity or opacity, but by a change of channel conductivity associated with atomic species being inserted or removed as a result of the stress signal.
The read operation is decoupled from the write operation thanks to the presence of three electrodes, therefore limiting read disturb. A small bias is applied between the channel electrodes, with the resulting read current being proportional to the channel conductivity, hence sensing the programmed state of the device.
The programming speed of ECRAM cells is not limited by the bulk diffusion of ions. They indeed only need to cross the interface plane between the electrolyte and the channel to induce a change in conductivity. Nanosecond write pulses can indeed trigger programming. Trade-offs between gate capacitance, electronic conductivity, etc., can yield settling transients, limiting the maximum read-write frequency.
ECRAM arrays are integrated in a pseudo-crossbar layout, the gate access line being common to all devices in a row or column. If a change in electrochemical potential, the driving force of a battery, occurs upon ionic exchange between channel and gate electrode, an open circuit potential (OCP) exists at the gate contact and will differ device to device depending on the programmed state. To prevent cross-talk between cells sharing a gate line, an access device to isolate each one is added in series with the memory element. Suppressing OCP in the ECRAM design, minimizes the cell size/complexity, allowing for selector-free parallel read/programming of device arrays.
Non-volatile memory (NVM) can be leveraged for in-memory compute, thereby reducing the frequency of data transfer between storage and processing units. This can ultimately improve compute time and energy efficiency over hierarchical system architectures by eliminating the Von Neumann bottleneck. Hence, when using multi-level cells (MLC) at the nodes of cross-bar arrays, one can perform analog operations on time or voltage encoded data such as vector (row input signal) × matrix (memory array) multiply. Following Kirchoff's and Ohm's laws, the resulting vector is then obtained by integrating the current collected at each column. For ECRAM cells, an additional line is added at each row to write the cells during programming cycles, thereby yielding a pseudo-crossbar architecture. In the field of artificial intelligence (A.I.), deep neural networks (DNN) are used for classification and learning tasks, relying on a large number of matrix-multiply operations. Therefore, analog compute with NVM technology for such tasks are extremely attractive. ECRAM cells are uniquely positioned for use in analog deep learning accelerators due to their inherent deterministic and symmetric programming nature when compared to other devices such as resistive RAM (ReRAM or RRAM) and phase-change memory (PCM).
|Metric||Unit||NVM synaptic |
|# of states||n.a.||1000|
Physical implementation of artificial neural networks (ANN) must perform at iso-accuracy when benchmarked against floating point precision weights in software. This sets the boundary for device properties needed for analog deep learning accelerators. In the design of their resisistive processing unit (RPU), IBM Research has published such requirements, a subset of which is listed here. Algorithm and hardware co-design can relax them somewhat but not without other trade-offs.
NVM use as synaptic weights in lieu of storage implies significantly different requirements when it comes to target resistance range, number of levels, and programming speed and symmetry. Because the in-memory computation occurs in parallel through the array, many devices are addressed concurrently and therefore need to have a high average resistance to limit energy dissipation. To perform high-accuracy computation and be resilient to noise, the NVM cell needs a large number of distinct states. The programming time needs only to be fast between levels, not from the highest to the lowest resistance states. During each programming cycle (back-propagation), weight updates can be negative or positive, and the up/down traces therefore need symmetry to allow learning algorithms to converge. All NVM technologies do struggle with these targets. ECRAM individual cells can meet such stringent metrics, but also need to demonstrate high-density array yield and stochasticity.
As reported in a 2019 publication in Science, by Elliot J. Fuller, Alec A. Talin, et al. from Sandia National Laboratories, in collaboration with Stanford University, and the University of Massachusetts Amherst:
Using co-planar organic multilevel cells, isolated by conductive bridge memory (CBM) devices, the team demonstrates parallel programming and addressing in up to 3×3 arrays. In particular a 2-layer neural network is mapped to the array by transferring the weights necessary to perform an inference task resulting in a XOR operation on the binary input vector.
Individual cells are shown to have the following properties (not all achieved in the same device configuration); speed = 1 MHz read-write cycles, number of states > 50 (tunable), resistance range = 50-100 nS (tunable), endurance > 108 write ops, size = 50×50 μm2.
As reported in a 2019 proceeding of the IEEE International Electron Device Meeting (IEDM), by Seyoung Kim, John Rozen, et al. from IBM Research:
Using metal-oxide ECRAM cells, selector-free, the team demonstrates parallel programming and addressing in 2×2 arrays. In particular, a logistic regression task is performed in-memory with 1,000 2×1 vectors as training set. 2D curve fit is achieved in a dozen epochs.
Individual cells are shown to have the following properties (not all achieved in the same device configuration); speed = 10 ns write pulses, number of states > 1,000 (tunable), resistance range = 0-50 μS (tunable), endurance > 107 write ops, size < 1×1 μm2.
Various institutions have demonstrated ECRAM cells with vastly different materials, layouts, and performances.
An example set for discrete cells is listed in the table.
|Ion||Channel||Device Size||Write Pulse Length||Reference|
|100 x 100 nm2||5 ns|||
|~1 mm2||0.5 s|||
||Graphene||36 μm2||10 ms|||
|~1 mm2||10 ms|||
||PEDOT:PSS||0.001 mm2||5 ms|||
|0.05 mm2||5 ms|||
|0.025 mm2||210 ms|||
|0.01 mm2||0.1 s|||
Based on lithium ions, Li-ECRAM devices have demonstrated repeatable and controlled switching by applying known materials from battery technology to the memory design. Consequently, such cells can exhibit an OCP which varies over several volts, depending on the programmed state.
Based on hydrogen ions, H-ECRAM devices have proven fast, necessitating small driving forces to induce programming. High diffusion coefficients in various materials can be accompanied by lack of retention within the memory cell, impacting endurance. Most H-ECRAM designs use liquid and/or organic electrolytes.
Metal-oxide based ECRAM, are inspired from OxRam materials and high-k/metal gate technology used in commercial semiconductor offerings. MO-ECRAM do enable negligible OCP and sub-μs write operations.
For advanced semiconductor memory or compute applications, a technology needs to be compatible with very large scale integration (VLSI). This puts constraints on materials used, and the techniques employed to fabricate functional devices. The implications for ECRAM are described here.
A semiconductor foundry can handle several technologies and has strict rules when it comes to materials being introduced in its expensive toolset to avoid cross-contamination and loss of device yield. In particular, metallic mobile ions, if present in active areas, can induce device drift and affect reliability. There are several other considerations for the foundries; including safety, cost, volume, etc. Hence, lithium ion-based Li-ECRAM faces unique challenges beyond the presence of OCP.
Memory arrays require logic periphery to operate and interface with the rest of the compute system. Such periphery is based on field-effect transistors (FETs) built on the surface of silicon wafer substrates with a high thermal budget at the front end of line (FEOL). Memory cells can be inserted between upper metal levels at back end of line (BEOL) but will still need to remain unaffected by temperatures up to ~400 °C used in subsequent steps. Together with high density patterning challenges, these restrictions make organic devices unsuitable for such integration.
One way to introduce novel memory materials can be to use heterogeneous integration (HI) where the device array is fabricated independently from the logic controls and then bonded to the FET-containing chip to enable its use as high bandwidth memory (HBM). However, the cost and complexity associated with such scheme negatively affects the value proposition for displacing existing memory technologies.