Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology.
SSSE3 was first introduced with Intel processors based on the Core microarchitecture on June 26, 2006 with the "Woodcrest" Xeons.
SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it.
SSSE3 has enhanced for HD audio/video decoding/encoding, for example AAC.
SSSE3 contains 16 new discrete instructions. Each instruction can act on 64bit MMX or 128bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. They include:^{[1]}
In the table below, satsw(X) (read as 'saturate to signed word') takes a signed integer X, and converts it to −32768 if it is less than −32768, to +32767 if it is greater than 32767, and leaves it unchanged otherwise. As normal for the Intel architecture, bytes are 8 bits, words 16 bits, and dwords 32 bits; 'register' refers to an MMX or XMM vector register.^{[1]}
Instruction  Definition  Explanation 

PSIGNB , PSIGNW , PSIGND

Packed Sign  Negate the elements of a register of bytes, words or dwords if the sign of the corresponding elements of another register is negative. 
PABSB , PABSW , PABSD

Packed Absolute Value  Fill the elements of a register of bytes, words or dwords with the absolute values of the elements of another register 
PALIGNR

Packed Align Right  take two registers, concatenate their values, and pull out a registerlength section from an offset given by an immediate value encoded in the instruction. 
PSHUFB

Packed Shuffle Bytes  takes registers of bytes A = [a_{0} a_{1} a_{2} ...] and B = [b_{0} b_{1} b_{2} ...] and replaces A with [a_{b0} a_{b1} a_{b2} ...]; except that it replaces the ith entry with 0 if the top bit of b_{i} is set. 
PMULHRSW

Packed Multiply High with Round and Scale  treat the 16bit words in registers A and B as signed 16bit fixedpoint numbers between −1.00000000 and +0.99996948... (e.g. 0x4000 is treated as +0.5 and 0xA000 as −0.75), and multiply them together with correct rounding. 
PMADDUBSW

Multiply and Add Packed Signed and Unsigned Bytes  Take the bytes in registers A and B, multiply them together, add pairs, signedsaturate and store. I.e. [a_{0} a_{1} a_{2} ...] PMADDUBSW [b_{0} b_{1} b_{2} ...] = [satsw(a_{0}b_{0} + a_{1}b_{1}) satsw(a_{2}b_{2} + a_{3}b_{3}) ...]

PHSUBW , PHSUBD

Packed Horizontal Subtract (Words or Doublewords)  takes registers A = [a_{0} a_{1} a_{2} ...] and B = [b_{0} b_{1} b_{2} ...] and outputs [a_{0}−a_{1} a_{2}−a_{3} ... b_{0}−b_{1} b_{2}−b_{3} ...] 
PHSUBSW

Packed Horizontal Subtract and Saturate Words  like PHSUBW, but outputs [satsw(a_{0}−a_{1}) satsw(a_{2}−a_{3}) ... satsw(b_{0}−b_{1}) satsw(b_{2}−b_{3}) ...] 
PHADDW , PHADDD

Packed Horizontal Add (Words or Doublewords)  takes registers A = [a_{0} a_{1} a_{2} ...] and B = [b_{0} b_{1} b_{2} ...] and outputs [a_{0}+a_{1} a_{2}+a_{3} ... b_{0}+b_{1} b_{2}+b_{3} ...] 
PHADDSW

Packed Horizontal Add and Saturate Words  like PHADDW, but outputs [satsw(a_{0}+a_{1}) satsw(a_{2}+a_{3}) ... satsw(b_{0}+b_{1}) satsw(b_{2}+b_{3}) ...] 