The list of Super NES enhancement chips demonstrates Nintendo hardware designers' plan to easily expand the Super Nintendo Entertainment System with special coprocessors. This standardized selection of chips was available to licensed developers, to increase system performance and features for each game cartridge. As increasingly superior chips became available throughout the Super NES's generation, this provided a cheaper and more versatile way of maintaining the system's market lifespan compared to Nintendo's option of having included a much more expensive CPU or a more obsolete stock chipset.
The presence of an enhancement chip is often indicated by 16 additional pins on either side of the original pins, 8 to each side.[1]
This chip has at least four revisions, first as a surface mounted chip labeled "MARIO CHIP 1" (Mathematical, Argonaut, Rotation & I/O), commonly called the Super FX, in the earliest Star Fox (1993) cartridges. From 1994, some boards have an epoxy version, and later a first revision is labeled GSU-1. Both versions are clocked with a 21.47 MHz signal, but an internal clock speed divider halves it to 10.74 MHz on the MARIO CHIP 1. The GSU-1 however runs at the full 21.47 MHz. Both the MARIO CHIP 1 and the GSU-1 can support a maximum ROM size of 8 Mbits. The design was revised to the GSU-2, which is still 16-bit, but this version can support a ROM size greater than 8 Mbit. The final known revision is the GSU-2-SP1. All versions of the Super FX chip are functionally compatible in terms of their instruction set. The differences are in packaging, pinout, maximum supported ROM size, and internal clock speed.[3]
Variants of the Super FX chip sorted chronologically.
The Cx4 chip is a math coprocessor used by Capcom and produced by Hitachi (now Renesas) to perform general trigonometric calculations for wireframe effects, sprite positioning, and rotation. It maps and transforms wireframes in Capcom's second and third games of the Mega Man X series.[2] It is based on the Hitachi HG51B169 DSP and clocked at 20 MHz.[4] The name Cx4 stands for Capcom Consumer Custom Chip.[5]
CX4 wireframe test screen
A Cx4 self-test screen can be accessed by holding the 'B' button on the second controller upon system start-up in both Mega Man X2 and X3.[6]
This series of fixed-point digital signal processor chips provides fast vector-based calculations, bitmap conversions, 2D and 3D coordinate transformations, and other functions.[7] The chip has four revisions, each physically identical but with different microcode. The DSP-1 version, including the later 1A die shrink and 1B bug fix revisions, was most often used; the DSP-2, DSP-3, and DSP-4 were used in only one game each.[8] All of them are based on the NEC µPD77C25 CPU and clocked at 8 MHz.[4]
DSP-1
The DSP-1 is the most varied and widely used of the Super NES DSPs, in more than 15 separate games. It is used as a math coprocessor in games such as Super Mario Kart and Pilotwings that require more advanced Mode 7 scaling and rotation. It provides fast support for the floating-point and trigonometric calculations needed by 3D math algorithms. The later DSP-1A and DSP-1B serve the same purpose as the DSP-1. The DSP-1A is a die shrink of the DSP-1, and the DSP-1B corrects several bugs.[9] The DSP-1B introduced a bug in the Pilotwings demo due to the game code not being updated for the timing differences of the chip revisions.[10]
DSP-2
The DSP-2 is only in Dungeon Master. Its primary purpose is to convert Atari STbitmap image data into the Super NES bitplane format. It also provides dynamic scaling capability and transparency effects.[11]
DSP-3
The DSP-3 is only in the turn-based strategy game SD Gundam GX for Super Famicom. It assists with tasks like calculating the next AI move, Shannon–Fano bitstream decompression, and bitplane conversion of graphics.[12]
DSP-4
TheDSP-4 is used in only Top Gear 3000. It primarily assists with drawing the race track, especially during the times that the track branches into multiple paths.
The hardware inside the Super Game Boy peripheral includes a Sharp SM83[13][14] core mostly identical to the CPU in the handheld Game Boy.[15] Because the Super NES is not powerful enough for software emulation of the Game Boy, the hardware for the entire handheld is inside of the cartridge.[16] Game Boy games however run approximately 2.4% faster than on an actual Game Boy due to a slightly higher clock speed.[17] The Super Game Boy 2, only released in Japan, fixes this.
This chip was made by MegaChips exclusively for Nintendo Power cartridges for the Super Famicom. The cartridges have flash ROMs instead of mask ROMs, to hold games downloaded for a fee at retail kiosks in Japan. The chip manages communication with the kiosks to download ROM images, and provides game selection menu. Some games were produced both in cartridge and download form, and others were download only. The service was closed in February 2007.[18]
The S-DD1 chip is an ASIC decompressor made by Nintendo for use in some Super Nintendo Entertainment System Game Paks.[2] Designed to handle data compressed by the ABS Lossless Entropy Algorithm, a form of arithmetic coding developed by Ricoh, its use is necessary in games where massive amounts of sprite data are compressed with a total design limit of 32-megabits. This data is decompressed dynamically by the S-DD1 and given directly to the picture processing unit.
The S-DD1 mediates between the Super NES's Ricoh 5A22 CPU and the game's ROM via two buses. However, the controlling 5A22 processor may still request normal, uncompressed data from the game's ROM even if the S-DD1 is already busy with a decompression operation. This form of parallelism allows sprite data to be decompressed while other types of data are quickly passed to the main CPU.
Star Ocean and Street Fighter Alpha 2 are the only games that use this chip. Emulation of the S-DD1 was initially difficult, requiring "graphics packs" to be provided for the affected games, until the compression algorithm was identified.[21][22]
Similar to the 5A22 CPU in the Super NES hardware, the SA1 contains a processor core based on the 65C816 with several programmable timers.[2] The SA1 does not function as a slave CPU for the 5A22; both can interrupt each other independently.
The SA1 also features a range of enhancements over the standard 65C816:
10.74 MHzclock speed, compared to the 5A22's maximum of 3.58 MHz
