A depletion-load NMOS NAND gate

In integrated circuits, depletion-load NMOS is a form of digital logic family that uses only a single power supply voltage, unlike earlier NMOS (n-type metal-oxide semiconductor) logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many microprocessors and other logic elements.

Depletion-mode n-type MOSFETs as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better current source approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early PMOS and NMOS chips demanded several voltages).

The inclusion of depletion-mode NMOS transistors in the manufacturing process demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of dopant in the load transistors channel region, in order to adjust their threshold voltage. This is normally performed using ion implantation.

Although the CMOS process replaced most NMOS designs during the 1980s, some depletion-load NMOS designs are still produced, typically in parallel with newer CMOS counterparts. One example of this is the Z84015[1] and Z84C15.[2]

History and background

See also: NMOS logic § History

Following the invention of the MOSFET by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959, they demonstrated MOSFET technology in 1960.[3] They fabricated both PMOS and NMOS devices with a 20 µm process. However, the NMOS devices were impractical, and only the PMOS type were practical working devices.[4]

In 1965, Chih-Tang Sah, Otto Leistiko and A.S. Grove at Fairchild Semiconductor fabricated several NMOS devices with channel lengths between 8 µm and 65 µm.[5] Dale L. Critchlow and Robert H. Dennard at IBM also fabricated NMOS devices in the 1960s. The first IBM NMOS product was a memory chip with 1 kb data and 50–100 ns access time, which entered large-scale manufacturing in the early 1970s. This led to MOS semiconductor memory replacing earlier bipolar and ferrite-core memory technologies in the 1970s.[6]

Silicon gate

In the late 1960s, bipolar junction transistors were faster than (p-channel) MOS transistors then used and were more reliable, but they also consumed much more power, required more area, and demanded a more complicated manufacturing process. MOS ICs were considered interesting but inadequate for supplanting the fast bipolar circuits in anything but niche markets, such as low power applications. One of the reasons for the low speed was that MOS transistors had gates made of aluminum which led to considerable parasitic capacitances using the manufacturing processes of the time. The introduction of transistors with gates of polycrystalline silicon (that became the de facto standard from the mid-1970s to early 2000s) was an important first step in order to reduce this handicap. This new self-aligned silicon-gate transistor was introduced by Federico Faggin at Fairchild Semiconductor in early 1968; it was a refinement (and the first working implementation) of ideas and work by John C. Sarace, Tom Klein and Robert W. Bower (around 1966–67) for a transistor with lower parasitic capacitances that could be manufactured as part of an IC (and not only as a discrete component). This new type of pMOS transistor was 3–5 times as fast (per watt) as the aluminum-gate pMOS transistor, and it needed less area, had much lower leakage and higher reliability. The same year, Faggin also built the first IC using the new transistor type, the Fairchild 3708 (8-bit analog multiplexer with decoder), which demonstrated a substantially improved performance over its metal-gate counterpart. In less than 10 years, the silicon gate MOS transistor replaced bipolar circuits as the main vehicle for complex digital ICs.

NMOS and back-gate bias

There are a couple of drawbacks associated with PMOS: The electron holes that are the charge (current) carriers in PMOS transistors have lower mobility than the electrons that are the charge carriers in NMOS transistors (a ratio of approximately 2.5), furthermore PMOS circuits do not interface easily with low voltage positive logic such as DTL-logic and TTL-logic (the 7400-series). However, PMOS transistors are relatively easy to make and were therefore developed first — ionic contamination of the gate oxide from etching chemicals and other sources can very easily prevent (the electron based) NMOS transistors from switching off, while the effect in (the electron-hole based) PMOS transistors is much less severe. Fabrication of NMOS transistors therefore has to be many times cleaner than bipolar processing in order to produce working devices.

Early work on NMOS integrated circuit (IC) technology was presented in a brief IBM paper at ISSCC in 1969. Hewlett-Packard then started to develop NMOS IC technology to get the promising speed and easy interfacing for its calculator business.[7] Tom Haswell at HP eventually solved many problems by using purer raw materials (especially aluminum for interconnects) and by adding a bias voltage to make the gate threshold large enough; this back-gate bias remained a de facto standard solution to (mainly) sodium contaminants in the gates until the development of ion implantation (see below). Already by 1970, HP was making good enough nMOS ICs and had characterized it enough so that Dave Maitland was able to write an article about nMOS in the December, 1970 issue of Electronics magazine. However, NMOS remained uncommon in the rest of the semiconductor industry until 1973.[8]

The production-ready NMOS process enabled HP to develop the industry’s first 4-kbit IC ROM. Motorola eventually served as a second source for these products and so became one of the first commercial semiconductor vendors to master the NMOS process, thanks to Hewlett-Packard. A while later, the startup company Intel announced a 1-kbit pMOS DRAM, called 1102, developed as a custom product for Honeywell (an attempt to replace magnetic core memory in their mainframe computers). HP’s calculator engineers, who wanted a similar but more robust product for the 9800 series calculators, contributed IC fabrication experience from their 4-kbit ROM project to help improve Intel DRAM’s reliability, operating-voltage, and temperature range. These efforts contributed to the heavily enhanced Intel 1103 1-kbit pMOS DRAM, which was the world’s first commercially available DRAM IC. It was formally introduced in October 1970, and became Intel’s first really successful product.[9]

Depletion-mode transistors

Characteristics of depletion-mode MOSFET

Early MOS logic had one transistor type, which is enhancement mode so that it can act as a logic switch. Since suitable resistors were hard to make, the logic gates used saturated loads; that is, to make the one type of transistor act as a load resistor, the transistor had to be turned always on by tying its gate to the power supply (the more negative rail for PMOS logic, or the more positive rail for NMOS logic). Since the current in a device connected that way goes as the square of the voltage across the load, it provides poor pullup speed relative to its power consumption when pulled down. A resistor (with the current simply proportional to the voltage) would be better, and a current source (with the current fixed, independent of voltage) better yet. A depletion-mode device with gate tied to the opposite supply rail is a much better load than an enhancement-mode device, acting somewhere between a resistor and a current source.

The first depletion-load NMOS circuits were pioneered and made by the DRAM manufacturer Mostek, which made depletion-mode transistors available for the design of the original Zilog Z80 in 1975–76.[10] Mostek had the ion implantation equipment needed to create a doping profile more precise than possible with diffusion methods, so that the threshold voltage of the load transistors could be adjusted reliably. At Intel, depletion load was introduced in 1974 by Federico Faggin, an ex-Fairchild engineer and later the founder of Zilog. Depletion-load was first employed for a redesign of one of Intel's most important products at the time, a +5V-only 1Kbit NMOS SRAM called the 2102 (using more than 6000 transistors[11]). The result of this redesign was the significantly faster 2102A, where the highest performing versions of the chip had access times of less than 100ns, taking MOS memories close to the speed of bipolar RAMs for the first time.[12]

Depletion-load NMOS processes were also used by several other manufacturers to produce many incarnations of popular 8-bit, 16-bit, and 32-bit CPUs. Similarly to early PMOS and NMOS CPU designs using enhancement mode MOSFETs as loads, depletion-load nMOS designs typically employed various types of dynamic logic (rather than just static gates) or pass transistors used as dynamic clocked latches. These techniques can enhance the area-economy considerably although the effect on the speed is complex. Processors built with depletion-load NMOS circuitry include the 6800 (in later versions[13]), the 6502, Signetics 2650, 8085, 6809, 8086, Z8000, NS32016, and many others (whether or not the HMOS processors below are included, as special cases).

A large number of support and peripheral ICs were also implemented using (often static) depletion-load based circuitry. However, there were never any standardized logic families in NMOS, such as the bipolar 7400 series and the CMOS 4000 series, although designs with several second source manufacturers often achieved something of a de facto standard component status. One example of this is the NMOS 8255 PIO design, originally intended as an 8085 peripheral chip, that has been used in Z80 and x86 embedded systems and many other contexts for several decades. Modern low power versions are available as CMOS or BiCMOS implementations, similar to the 7400-series.

Intel HMOS

Intel's own depletion-load NMOS process was known as HMOS, for High density, short channel MOS. The first version was introduced in late 1976 and first used for their static RAM products,[14] it was soon being used for faster and/or less power hungry versions of the 8085, 8086, and other chips.

HMOS continued to be improved and went through four distinct generations. According to Intel, HMOS II (1979) provided twice the density and four times the speed/power product over other typical contemporary depletion-load NMOS processes.[15] This version was widely licensed by 3rd parties, including (among others) Motorola who used it for their Motorola 68000, and Commodore Semiconductor Group, who used it for their MOS Technology 8502 die-shrunk MOS 6502.

The original HMOS process, later referred to as HMOS I, had a channel length of 3 microns, which was reduced to 2 for the HMOS II, and 1.5 for HMOS III. By the time HMOS III was introduced in 1982, Intel had begun a switch to their CHMOS process, a CMOS process using design elements of the HMOS lines. One final version of the system was released, HMOS-IV. A significant advantage to the HMOS line was that each generation was deliberately designed to allow existing layouts to die-shrink with no major changes. Various techniques were introduced to ensure the systems worked as the layout changed.[16][17]

HMOS, HMOS II, HMOS III, and HMOS IV were together used for many different kinds of processors; the 8085, 8048, 8051, 8086, 80186, 80286, and many others, but also for several generations of the same basic design, see datasheets.

Further development

In the mid-1980s, faster CMOS variants, using similar HMOS process technology, such as Intel's CHMOS I, II, III, IV, etc. started to supplant n-channel HMOS for applications such as the Intel 80386 and certain microcontrollers. A few years later, in the late 1980s, BiCMOS was introduced for high-performance microprocessors as well as for high speed analog circuits. Today, most digital circuits, including the ubiquitous 7400 series, are manufactured using various CMOS processes with a range of different topologies employed. This means that, in order to enhance speed and save die area (transistors and wiring), high speed CMOS designs often employ other elements than just the complementary static gates and the transmission gates of typical slow low-power CMOS circuits (the only CMOS type during the 1960s and 1970s). These methods use significant amounts of dynamic circuitry in order to construct the larger building blocks on the chip, such as latches, decoders, multiplexers, and so on, and evolved from the various dynamic methodologies developed for NMOS and PMOS circuits during the 1970s.

Compared to CMOS

Compared to static CMOS, all variants of NMOS (and PMOS) are relatively power hungry in steady state. This is because they rely on load transistors working as resistors, where the quiescent current determines the maximum possible load at the output as well as the speed of the gate (i.e. with other factors constant). This contrasts to the power consumption characteristics of static CMOS circuits, which is due only to the transient power draw when the output state is changed and the p- and n-transistors thereby briefly conduct at the same time. However, this is a simplified view, and a more complete picture has to also include the fact that even purely static CMOS circuits have significant leakage in modern tiny geometries, as well as the fact that modern CMOS chips often contain dynamic and/or domino logic with a certain amount of pseudo nMOS circuitry.[18]

Evolution from preceding NMOS types

Depletion-load processes differ from their predecessors in the way the Vdd voltage source, representing 1, connects to each gate. In both technologies, each gate contains one NMOS transistor which is permanently turned on and connected to Vdd. When the transistors connecting to 0 turn off, this pull-up transistor determines the output to be 1 by default. In standard NMOS, the pull-up is the same kind of transistor as is used for logic switches. As the output voltage approaches a value less than Vdd, it gradually switches itself off. This slows the 0 to 1 transition, resulting in a slower circuit. Depletion-load processes replace this transistor with a depletion-mode NMOS at a constant gate bias, with the gate tied directly to the source. This alternative type of transistor acts as a current source until the output approaches 1, then acts as a resistor. The result is a faster 0 to 1 transition.

Static power consumption

An NMOS NAND gate with saturated enhancement-mode load device. The enhancement device can also be used with a more positive gate bias in a non-saturated configuration, which is more power efficient but requires a high gate voltage and a longer transistor. Neither is as power efficient or compact as a depletion load.

Depletion-load circuits consume less power than enhancement-load circuits at the same speed. In both cases the connection to 1 is always active, even when the connection to 0 is also active. This results in high static power consumption. The amount of waste depends on the strength, or physical size, of the pull-up. Both (enhancement-mode) saturated-load and depletion-mode pull-up transistors use greatest power when the output is stable at 0, so this loss is considerable. Because the strength of a depletion-mode transistor falls off less on the approach to 1, they may reach 1 faster despite starting slower, i.e. conducting less current at the beginning of the transition and at steady state.

Notes and references

  1. ^ See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84015.
  2. ^ See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84C15.
  3. ^ "1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated". The Silicon Engine. Computer History Museum.
  4. ^ Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. pp. 321–3. ISBN 9783540342588.
  5. ^ Sah, Chih-Tang; Leistiko, Otto; Grove, A. S. (May 1965). "Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces". IEEE Transactions on Electron Devices. 12 (5): 248–254. Bibcode:1965ITED...12..248L. doi:10.1109/T-ED.1965.15489.
  6. ^ Critchlow, D. L. (2007). "Recollections on MOSFET Scaling". IEEE Solid-State Circuits Society Newsletter. 12 (1): 19–22. doi:10.1109/N-SSC.2007.4785536.
  7. ^ These calculators (like the Datapoint 2200 and others) were in many ways small desktop computers, but preceded the Apple II and the IBM PC by many years.
  8. ^ Shown by its mere mention in a large roundup article written by GE engineer Herman Schmid that appeared in the December, 1972 issue of IEEE Transactions on Manufacturing Technology. Although it cites Maitland’s 1970 article in Electronics, Schmid’s article does not discuss NMOS fabrication in detail but it does cover PMOS and even CMOS fabrication extensively.
  9. ^ "Prologues". Hp9825.com. Retrieved 2022-03-15.
  10. ^ Zilog relied on Mostek and Synertek to produce the Z80 and other chips before their own production facilities were ready.
  11. ^ Each bit demands six transistors in a typical static RAM.
  12. ^ See for instance: http://www.intel4004.com/sgate.htm or http://archive.computerhistory.org/resources/text/Oral_History/Faggin_Federico/Faggin_Federico_1_2_3.oral_history.2004.102658025.pdf Archived 2017-01-10 at the Wayback Machine
  13. ^ "Motorola Redesigns 6800" (PDF). Microcomputer Digest. 3 (2). Santa Clara, CA: Microcomputer Associates: 4. August 1976. "Motorola is redesigning the M6800 microprocessor family by adding depletion loads to increase speed and reduce the 6800 CPU size to 160 mils."
  14. ^ Volk, A.M.; Stoll, P.A.; Metrovich, P. (2001). "Recollections of Early Chip Development at Intel" (PDF). Intel Technology Journal. 5 (Q1).
  15. ^ See for instance: Scanlon, Leo J.; Moody, C.W. (1981). The 68000 Principles and programming. H.W. Sams. ISBN 978-0-672-21853-8. OCLC 7802969.
  16. ^ HMOS III Technology. ISSCC 82. 1982.
  17. ^ Atwood, G.E.; Dun, H.; Langston, J.; Hazani, E.; So, E.Y.; Sachdev, S.; Fuchs, K. (October 1982). "HMOS III technology". IEEE Journal of Solid-State Circuits. 17 (5): 810–5. Bibcode:1982IJSSC..17..810A. doi:10.1109/JSSC.1982.1051823. S2CID 1215664.
  18. ^ Pseudo nMOS means that an enhancement-mode p-channel transistor with grounded gate is used in place of the depletion-mode n-channel transistor. See http://eia.udg.es/~forest/VLSI/lect.10.pdf