In computing, Direct Media Interface (DMI) is Intel's proprietary link between the northbridge (or CPU) and southbridge (e.g. Platform Controller Hub family) chipset on a computer motherboard.^[1] It was first used between the 9xx chipsets and the ICH6, released in 2004.^[2]: 1 Previous Intel chipsets had used the Intel Hub Architecture to perform the same function, and server chipsets use a similar interface called Enterprise Southbridge Interface (ESI).^[3] While the "DMI" name dates back to ICH6, Intel mandates specific combinations of compatible devices, so the presence of a DMI does not guarantee by itself that a particular northbridge–southbridge combination is allowed.

DMI is essentially PCI Express, using multiple lanes and differential signaling to form a point-to-point link. Most implementations use a ×8 or ×4 link, while some mobile systems (e.g. 915GMS, 945GMS/GSE/GU and the Atom N450) use a ×2 link, halving the bandwidth. The original implementation provides 10 Gbit/s (1 GB/s) in each direction using a ×4 link. The DMI provides support for concurrent traffic and isochronous data transfer capabilities.^{[2]: 3 [4]}

Versions

DMI 1.0, introduced in 2004 with a data transfer rate of 1GB/s with a ×4 link.

DMI 2.0, introduced in 2011, doubles the data transfer rate to 2 GB/s with a ×4 link. It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge.^[5]: 14

DMI 3.0, released in August 2015, allows the 8 GT/s transfer rate per lane, for a total of four lanes and 3.93 GB/s for the CPU–PCH link. It is used by two-chip variants of the Intel Skylake microprocessors, which are used in conjunction with Intel 100 Series chipsets;^[6][7] some low power (Skylake-U onwards) and ultra low power (Skylake-Y onwards) mobile Intel processors have the PCH integrated into the physical package as a separate die, referred to as OPI (On Package DMI interconnect Interface)^[8] and effectively following the system on a chip (SoC) design layout.^[9] On 9 March 2015, Intel announced the Broadwell-based Xeon D as its first enterprise platform to fully incorporate the PCH in an SoC configuration.^[10]

In 2021, with the release of 500 series chipsets, Intel increased the amount of DMI 3.0 lanes from four to eight, doubling the bandwidth.^[11]

DMI 4.0, released on November 4, 2021 with 600 series chipsets, doubles the bandwidth each lane provides and is two times faster when compared to DMI 3.0. The number of DMI 4.0 lanes depends on chipset model used.^[12]

Implementations

2005 Centrino mobile platform.^[2]: 3 At the time DMI linked the GMCH and I/O Controller Hub.^[2]: 3

Northbridge devices supporting a northbridge DMI are the Intel 915-series, 925-series, 945-series, 955-series, 965-series, 975-series, G31/33, P35, X38, X48, P45 and X58.^{[citation needed]}

Processors supporting a northbridge DMI and, therefore, not using a separate northbridge, are the Intel Atom, Intel Core i3, Intel Core i5, and Intel Core i7 (8xx, 7xx and 6xx, but not 9xx). Processors supporting a northbridge DMI 2.0 and, therefore not using a separate northbridge, are the 2000, 3000, 4000, and 5000 series of the Intel Core i3, Core i5 and Core i7.

Southbridge devices supporting a southbridge DMI are the ICH6, ICH7, ICH8, ICH9, ICH10, NM10, P55, H55, H57, Q57, PM55, HM55, HM57, QM57 and QS57.^{[citation needed]}

PCH devices supporting DMI 2.0 are the Intel B65, H61, H67, P67, Q65, Q67, Z68, HM65, HM67, QM67, QS67, B75, H77, Q75, Q77, Z75, Z77, X79, HM75, HM76, HM77, QM77, QS77, UM77, H81, B85, Q85, Q87, H87, Z87, H97, Z97, C222, C224, C226, X99, H110,^[13] and H310.^[14]

PCH devices supporting DMI 3.0 are the Intel Z170, H170, HM170, Q170, QM170, Q150, B150, C236, CM236, C232, and C620.^{[15][16][17][18][19][20][21][22][23][24]} The Intel 200 series, B360,^[25] H370,^[26] Q370,^[27] Z370,^[28] Z390,^[29] C246,^[30] and Intel 400 series chipsets also support DMI 3.0.

PCH devices supporting DMI 4.0 are the Intel 600 and 700 Series chipsets.^[31][32]