Interface used for connecting storage devices
NVM Express|
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| Abbreviation | NVMe |
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| Status | Published |
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| Year started | 2011; 13 years ago (2011) |
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| Latest version | 2.0c
October 2022[1] |
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| Organization | NVM Express Work Group (incorporated as NVM Express in 2014) |
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| Website | nvmexpress.org |
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NVM Express (NVMe) or Non-Volatile Memory Host Controller Interface Specification (NVMHCIS) is an open, logical-device interface specification for accessing a computer's non-volatile storage media usually attached via the PCI Express bus. The initial NVM stands for non-volatile memory, which is often NAND flash memory that comes in several physical form factors, including solid-state drives (SSDs), PCIe add-in cards, and M.2 cards, the successor to mSATA cards. NVM Express, as a logical-device interface, has been designed to capitalize on the low latency and internal parallelism of solid-state storage devices.[2]
Architecturally, the logic for NVMe is physically stored within and executed by the NVMe controller chip that is physically co-located with the storage media, usually an SSD. Version changes for NVMe, e.g., 1.3 to 1.4, are incorporated within the storage media, and do not affect PCIe-compatible components such as motherboards and CPUs.[3]
By its design, NVM Express allows host hardware and software to fully exploit the levels of parallelism possible in modern SSDs. As a result, NVM Express reduces I/O overhead and brings various performance improvements relative to previous logical-device interfaces, including multiple long command queues, and reduced latency. The previous interface protocols like AHCI were developed for use with far slower hard disk drives (HDD) where a very lengthy delay (relative to CPU operations) exists between a request and data transfer, where data speeds are much slower than RAM speeds, and where disk rotation and seek time give rise to further optimization requirements.
NVM Express devices are chiefly available in the form of standard-sized PCI Express expansion cards[4] and as 2.5-inch form-factor devices that provide a four-lane PCI Express interface through the U.2 connector (formerly known as SFF-8639).[5][6] Storage devices using SATA Express and the M.2 specification which support NVM Express as the logical-device interface are a popular use-case for NVMe and have become the dominant form of solid-state storage for servers, desktops, and laptops alike.[7][8]
Specifications
Specifications for NVMe released to date include:[9]
- 1.0e (January 2013)
- 1.1b (July 2014)
- 1.2 (November 2014)
- 1.2a (October 2015)
- 1.2b (June 2016)
- 1.2.1 (June 2016)
- 1.3 (May 2017)
- 1.3a (October 2017)
- 1.3b (May 2018)
- 1.3c (May 2018)
- 1.3d (March 2019)
- 1.4 (June 2019)
- 1.4a (March 2020)
- 1.4b (September 2020)
- 1.4c (June 2021)
- 2.0 (May 2021)[10]
- 2.0a (July 2021)
- 2.0b (January 2022)
- 2.0c (October 2022)
Background
Historically, most SSDs used buses such as SATA, SAS, or Fibre Channel for interfacing with the rest of a computer system. Since SSDs became available in mass markets, SATA has become the most typical way for connecting SSDs in personal computers; however, SATA was designed primarily for interfacing with mechanical hard disk drives (HDDs), and it became increasingly inadequate for SSDs, which improved in speed over time.[11] For example, within about five years of mass market mainstream adoption (2005–2010) many SSDs were already held back by the comparatively slow data rates available for hard drives—unlike hard disk drives, some SSDs are limited by the maximum throughput of SATA.
High-end SSDs had been made using the PCI Express bus before NVMe, but using non-standard specification interfaces. By standardizing the interface of SSDs, operating systems only need one common device driver to work with all SSDs adhering to the specification. It also means that each SSD manufacturer does not have to design specific interface drivers. This is similar to how USB mass storage devices are built to follow the USB mass-storage device class specification and work with all computers, with no per-device drivers needed.[12]
NVM Express devices are also used as the building block of the burst buffer storage in many leading supercomputers, such as Fugaku Supercomputer, Summit Supercomputer and Sierra Supercomputer, etc.[13][14]
History
The first details of a new standard for accessing non-volatile memory emerged at the Intel Developer Forum 2007, when NVMHCI was shown as the host-side protocol of a proposed architectural design that had Open NAND Flash Interface Working Group (ONFI) on the memory (flash) chips side.[15] A NVMHCI working group led by Intel was formed that year. The NVMHCI 1.0 specification was completed in April 2008 and released on Intel's web site.[16][17][18]
Technical work on NVMe began in the second half of 2009.[19] The NVMe specifications were developed by the NVM Express Workgroup, which consists of more than 90 companies; Amber Huffman of Intel was the working group's chair. Version 1.0 of the specification was released on 1 March 2011,[20] while version 1.1 of the specification was released on 11 October 2012.[21] Major features added in version 1.1 are multi-path I/O (with namespace sharing) and arbitrary-length scatter-gather I/O. It is expected that future revisions will significantly enhance namespace management.[19] Because of its feature focus, NVMe 1.1 was initially called "Enterprise NVMHCI".[22] An update for the base NVMe specification, called version 1.0e, was released in January 2013.[23] In June 2011, a Promoter Group led by seven companies was formed.
The first commercially available NVMe chipsets were released by Integrated Device Technology (89HF16P04AG3 and 89HF32P08AG3) in August 2012.[24][25] The first NVMe drive, Samsung's XS1715 enterprise drive, was announced in July 2013; according to Samsung, this drive supported 3 GB/s read speeds, six times faster than their previous enterprise offerings.[26] The LSI SandForce SF3700 controller family, released in November 2013, also supports NVMe.[27][28] A Kingston HyperX "prosumer" product using this controller was showcased at the Consumer Electronics Show 2014 and promised similar performance.[29][30] In June 2014, Intel announced their first NVM Express products, the Intel SSD data center family that interfaces with the host through PCI Express bus, which includes the DC P3700 series, the DC P3600 series, and the DC P3500 series.[31] As of November 2014[update], NVMe drives are commercially available.
In March 2014, the group incorporated to become NVM Express, Inc., which as of November 2014[update] consists of more than 65 companies from across the industry. NVM Express specifications are owned and maintained by NVM Express, Inc., which also promotes industry awareness of NVM Express as an industry-wide standard. NVM Express, Inc. is directed by a thirteen-member board of directors selected from the Promoter Group, which includes Cisco, Dell, EMC, HGST, Intel, Micron, Microsoft, NetApp, Oracle, PMC, Samsung, SanDisk and Seagate.[32]
In September 2016, the CompactFlash Association announced that it would be releasing a new memory card specification, CFexpress, which uses NVMe.[citation needed]
NVMe Host Memory Buffer (HMB) added in version 1.2 of the NVMe specification.[33] HMB allows SSDs to utilize the host's DRAM, which can improve the I/O performance for DRAM-less SSDs.[34]
Form factors
There are many form factors of NVMe solid-state drive, such as AIC, U.2, U.3, M.2 etc.
AIC (add-in card)
Almost all early NVMe solid-state drives are HHHL (half height, half length) or FHHL (full height, half length) AIC, with a PCIe 2.0 or 3.0 interface. A HHHL NVMe solid-state drive card is easy to insert into a PCIe slot of a server.
U.2 (SFF-8639)
U.2, formerly known as SFF-8639, is a computer interface for connecting solid-state drives to a computer. It uses up to four PCI Express lanes. Available servers can combine up to 48 U.2 NVMe solid-state drives.[35]
U.3 (SFF-8639 or SFF-TA-1001)
U.3 is built on the U.2 spec and uses the same SFF-8639 connector. It is a 'tri-mode' standard, combining SAS, SATA and NVMe support into a single controller. U.3 can also support hot-swap between the different drives where firmware support is available. U.3 drives are still backward compatible with U.2, but U.2 drives are not compatible with U.3 hosts.
M.2
M.2, formerly known as the Next Generation Form Factor (NGFF), uses a M.2 NVMe solid-state drive computer bus. Interfaces provided through the M.2 connector are PCI Express 3.0 or higher (up to four lanes).
EDSFF
NVMe-oF
NVM Express over Fabrics (NVMe-oF) is the concept of using a transport protocol over a network to connect remote NVMe devices, contrary to regular NVMe where physical NVMe devices are connected to a PCIe bus either directly or over a PCIe switch to a PCIe bus. In August 2017, a standard for using NVMe over Fibre Channel (FC) was submitted by the standards organization International Committee for Information Technology Standards (ICITS), and this combination is often referred to as FC-NVMe or sometimes NVMe/FC.[36]
As of May 2021, supported NVMe transport protocols are:
The standard for NVMe over Fabrics was published by NVM Express, Inc. in 2016.[41][42]
The following software implements the NVMe-oF protocol:
Comparison with AHCI
The Advanced Host Controller Interface (AHCI) has the benefit of wide software compatibility, but has the downside of not delivering optimal performance when used with SSDs connected via the PCI Express bus. As a logical-device interface, AHCI was developed when the purpose of a host bus adapter (HBA) in a system was to connect the CPU/memory subsystem with a much slower storage subsystem based on rotating magnetic media. As a result, AHCI introduces certain inefficiencies when used with SSD devices, which behave much more like RAM than like spinning media.[7]
The NVMe device interface has been designed from the ground up, capitalizing on the lower latency and parallelism of PCI Express SSDs, and complementing the parallelism of contemporary CPUs, platforms and applications. At a high level, the basic advantages of NVMe over AHCI relate to its ability to exploit parallelism in host hardware and software, manifested by the differences in command queue depths, efficiency of interrupt processing, the number of uncacheable register accesses, etc., resulting in various performance improvements.[7][49]: 17–18
The table below summarizes high-level differences between the NVMe and AHCI logical-device interfaces.
High-level comparison of AHCI and NVMe[7]
|
|
AHCI
|
NVMe
|
| Maximum queue depth
|
One command queue;
Up to 32 commands per queue |
Up to 65535 queues;[50]
Up to 65536 commands per queue
|
Uncacheable register accesses
(2000 cycles each)
|
Up to six per non-queued command;
Up to nine per queued command |
Up to two per command
|
| Interrupt
|
A single interrupt |
Up to 2048 MSI-X interrupts
|
Parallelism
and multiple threads
|
Requires synchronization lock
to issue a command |
No locking
|
Efficiency
for 4 KB commands
|
Command parameters require
two serialized host DRAM fetches |
Gets command parameters
in one 64-byte fetch
|
| Data transmission
|
Usually half-duplex |
Full-duplex
|
