In personal computer microprocessor architecture, a back-side bus (BSB), or backside bus, was a computer bus used on early Intel platforms to connect the CPU to CPU cache memory, usually off-die L2. If a design utilizes a back-side bus along with a front-side bus (FSB), the design is said to use a dual-bus architecture, or in Intel's terminology Dual Independent Bus (DIB)[1] architecture. The back-side bus architecture evolved when newer processors like the second-generation Pentium III began to incorporate on-die L2 cache, which at the time was advertised as Advanced Transfer Cache, but Intel continued to refer to the Dual Independent Bus till the end of Pentium III.[2]


BSB is an improvement over the older practice of using a single system bus, because a single bus typically became a severe bottleneck as CPUs and memory speeds increased. Due to its dedicated nature, the back-side bus can be optimized for communication with cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose bus. Furthermore, since a BSB operates over a shorter distance, it can typically operate at higher clock speeds, increasing the computer's overall performance.

Cache connected with a BSB was initially external to the microprocessor die, but now is usually on-die.[3] In the latter case, the BSB clock frequency is typically equal to the processor's,[4] and the back-side bus can also be made much wider (256-bit, 512-bit) than either off-chip or on-chip FSB.[clarification needed]

A Pentium II processor module with its cover removed showing the processor on the left and the L2 cache memory on the right

The dual-bus architecture was used in a number of designs, including the IBM and Freescale (formerly the semiconductor division of Motorola) PowerPC processors (certain PowerPC 604 models, the PowerPC 7xx family,[5] and the Freescale 7xxx line), as well as the Intel Pentium Pro, Pentium II and early Pentium III processors,[6] which used it to access their L2 cache (earlier Intel processors accessed the L2 cache over the FSB, while later processors moved it on-chip).

See also


  1. ^ "Dedicated Backside Cache Bus". 2001-04-30.
  2. ^ Pentium® III Processors for Applied Computing product brief
  3. ^ "Buses: frontside and backside". ITworld. 2001-04-30. Archived from the original on 2001-05-02.
  4. ^ "Buses: frontside and backside". ITworld. 2001-04-30. Archived from the original on 2001-05-02.
  5. ^ "Monday a big day for Apple". CNet. 1997-11-07.
  6. ^ "Backside Bus". 2001-04-30.